Coprocessor instructions and coprocessor id specification

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sporniket
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Coprocessor instructions and coprocessor id specification

Post by sporniket »

Hello,

I am studying the 68k instruction set using the MC68000 programmer's manual, and arriving to the coprocessor instructions (cpBcc, cpDBcc, cpGEN, etc...), I am a bit puzzled about how the coprocessor id is specified to generate the appropriate opcode.

I can see how vasm do it to support PMMU and FPU here : http://sun.hasenbraten.de/vasm/release/vasm_21.html ; where it tells that PMMU use cpId 0 and the FPU cpId is set using the 'fpu <cpID>' command line switch, and using prefix 'F' and 'P' instead of 'cp' (and then a quick check in the programmer's manual at the floating point instruction summary and I see e.g. FBcc, FDBcc, etc... and a specific instruction like e.g. FABS does use the cpGEN opcode followed by the coprocessor instruction word)

But there is nothing for when using other coprocessors (I understand that cpId 0 is reserved for the PMMU starting from the 68030 and is illegal for the 68020, that cpId 1 to 5 are reserved for Motorola coprocessors, and cpId 6 to 7 are reserved for 'user coprocessors')

Well, to my knowledge, I believe that Motorola did not created other coprocessors beyond the FPU and the MMU (MC68851), and I am not aware of any manufacturer having created one either, so the use of those instructions in assembly language is likely none, but how an hypothetical manufacturer of a coprocessor (as a user coprocessor, so id 6 or 7) implementing the coprocessor interface would target it without being able to specify the coprocessor id in the assembly language ?

Thanks in advance.
ThorstenOtto
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Re: Coprocessor instructions and coprocessor id specification

Post by ThorstenOtto »

Its just a matter of the how the assembler handles that. Only thing that is specified is that Line-F opcodes are used for it, and how the ID is encoded in that opcode. Addressing modes are already different (only the FPU cares about FPU register numbers). So before an assembler can support that, it would have to know which coprocessor to target.

Of course its always possible to make up you own pseudo-opcodes, using macros. Unfortunately macro syntax is quite different between assemblers on Atari.
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