FPGA implementation of 68020

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gary36
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FPGA implementation of 68020

Post by gary36 »

looking for VHDL/verilog code of 68020 processor.
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farvardin
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Re: FPGA implementation of 68020

Post by farvardin »

you can find this on the minimig project: https://github.com/rkrajnc/minimig-mist

probably there too: https://opencores.org/projects/tg68kc
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Re: FPGA implementation of 68020

Post by gary36 »

I am just a beginner. There are so any files. Please let me know where to look into. I am also looking for self checking testbench for 68020.
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Re: FPGA implementation of 68020

Post by slingshot »

The latest from TobiFlex:
https://github.com/TobiFlex/TG68K.C

It has some missing pieces, and the bus is 16 bit only, but still the most compatible 68020 available.

Testbench? That doesn't exist.
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Re: FPGA implementation of 68020

Post by gary36 »

Can anybody explain the microarchitecture of the soft core processor?
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Re: FPGA implementation of 68020

Post by stormy »

gary36 wrote: Wed Nov 03, 2021 2:57 pm Can anybody explain the microarchitecture of the soft core processor?
You realise you can directly ask the guy who wrote it?
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Re: FPGA implementation of 68020

Post by gary36 »

I could locate 68k patents . but finding difficult to find patents for 68020. Could anybody provide the link?
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Re: FPGA implementation of 68020

Post by mfro »

This might help if you want to learn: https://www.jwhitham.org/ri/pr3-40189.pdf

It's not a complete '020 (and no microcode implementation), but it starts at the beginning.
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Re: FPGA implementation of 68020

Post by mfro »

... excuse the double post :?
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Re: FPGA implementation of 68020

Post by gary36 »

I have seen the above link. However for full 68020 compatibility, microcode is required. Behavioral implementation will be tenuous
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Re: FPGA implementation of 68020

Post by sporniket »

What is your purpose exactly ?

Being a beginner myself in VHDL, I find it quite big to tackle directly a CPU model like one of the 68k family.

ijor retro-engineered the 68k, with microcode, cycle exact timings etc... https://github.com/ijor/fx68k
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Re: FPGA implementation of 68020

Post by gary36 »

My purpose is to replace 68020 for a legacy system. I understood from various sources that the micro-architecture for 68000 and 68020 are identical ( except for some fancy features such as dynamic bus sizing, cache etc) and they differ only in microcode. So looking for the same.
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Re: FPGA implementation of 68020

Post by mfro »

gary36 wrote: Tue Nov 30, 2021 4:38 am ... I understood from various sources that the micro-architecture for 68000 and 68020 are identical ( except for some fancy features such as dynamic bus sizing, cache etc) and they differ only in microcode...
I would seriously doubt that.

The 68020 is much more sophisticated than the (rather simple) 68000. Unlike the '000, the '020 has a 3-stage pipelined architecture and additional complex adressing modes (both documented in the UM). Just like the '030.
I would assume the internal architecture much more comparable to an 'unfinished 68030' than to the 68000. Or roughly: 68020 + 68851 = 68030.

There's no guarantee, but I would also assume cycle exactness isn't a strict requirement if you want to replace a real 68020 with an FPGA implementation. As long as your replacement cleanly implements the documented bus protocol, you should be good to go.
This assumption is based on the pipelined architecture together with the processor caches. These make the '020 runtime performance somehow non-deterministic already (similar to modern processor architectures): you can't really tell what the real runtime of a certain instruction sequence will be unless you specifically prepared your code upfront (i.e. flush instruction pipe and caches).

Anyway, implementation of a '020 (cycle exact or not) will be a steep learning curve for a HDL/FPGA beginner. Good luck with that!
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Re: FPGA implementation of 68020

Post by gary36 »

Ok. I got it. Ho do we go about bench marking the performance of 68k processor?
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