Has anyone tried to port the Defender Arcade core to MiST?
If this is ported, it should be easy to support Robotron, and Joust also.
I am trying, but I cannot figure out what the different Clock rates shall be?
(I cannot check the pll wizard, as the Project is for Cyclone V, and the version of Quartus II used for MiST will give an several errors when trying to load the Project)
Code: Select all
105 pll pll
107 .refclk(CLK_50M), //// This one is obvious 50 MHz, for MiST it should be 54 MHz
109 .outclk_0(clk_48), //// 48 MHz?
110 .outclk_1(clk_sys), //// What is this Clock rate?
111 .outclk_2(clk_6p), //// What is this Clock rate, phase shift etc?
115 apll apll
119 .outclk_0(clk_1p79), //// Another Clock I cannot determine the rate of, name makes it hard to guess?
120 .outclk_1(clk_0p89) //// Another Clock I cannot determine the rate of, name makes it hard to guess?
Also the Project seems to use a lot of block ram on the FPGA, however, it should be possible to use SDRAM for the ROM image at least.