Minimig (Amiga) core discussion

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Re: Minimig (Amiga) core discussion

Postby NegSol » Mon Jan 14, 2019 7:07 pm

albconde wrote:In my case the problem with adf with kick rom 1.3 start in comit f344ac9 (Fix the warnings).


Great find. Yes - it is a combination of MiSTer (binary) and Kick.rom (pre-2.04) that stops adfs from being recognized.

Your test MiSTer binary solves the issue. :mrgreen:

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Re: Minimig (Amiga) core discussion

Postby Sorgelig » Mon Jan 14, 2019 8:09 pm

I will test with Kick 1.3. At least there is a clue. I use Kick 3.1 as i use dual-boot Amiga.

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Re: Minimig (Amiga) core discussion

Postby Sorgelig » Mon Jan 14, 2019 8:41 pm

Will be fixed in next release.

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Re: Minimig (Amiga) core discussion

Postby PsyFX » Mon Jan 14, 2019 10:32 pm

albconde wrote:In my case the problem with adf with kick rom 1.3 start in comit f344ac9 (Fix the warnings).

The problem is with the variable dsklen , in minimig_fdd.cpp .

If uncoment the three lines (169, 204 and 221 ) in this file, and compile MiSTer file (last version) , the adf load.

In the attachments i put a version of last mister (release 20190112) with this changes , some other people with the problem of adf not loading can test this version ?


Thanks albconde! =)
Your "test build" of Minimig works as normal (loading ADFs), just did some preliminary tests with kickstart 1.2, 1.3
Still I wonder why only a few were effected.

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Re: Minimig (Amiga) core discussion

Postby NegSol » Mon Jan 14, 2019 11:14 pm

PsyFX wrote:Your "test build" of Minimig works as normal (loading ADFs), just did some preliminary tests with kickstart 1.2, 1.3
Still I wonder why only a few were effected.


I guess not everybody tests all kickstart versions all the time. Most use hdds and therefor cannot use the real old kickroms.

Anyway, thanks for finding and fixing, Sorgelig. :cheers:

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Re: Minimig (Amiga) core discussion

Postby Paradroyd » Tue Jan 15, 2019 2:36 am

Sorgelig wrote:Will be fixed in next release.


Thanks!
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Re: Minimig (Amiga) core discussion

Postby PsyFX » Tue Jan 15, 2019 3:05 am

NegSol wrote:
PsyFX wrote:Your "test build" of Minimig works as normal (loading ADFs), just did some preliminary tests with kickstart 1.2, 1.3
Still I wonder why only a few were effected.


I guess not everybody tests all kickstart versions all the time. Most use hdds and therefor cannot use the real old kickroms.

Anyway, thanks for finding and fixing, Sorgelig. :cheers:


I am just using what I know (for now), I never had a HD when I actually owned an Amiga :angel:

And Thanks getting this fixed in the next official release Sorgelig

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Re: Minimig (Amiga) core discussion

Postby Paradroyd » Tue Jan 15, 2019 5:11 am

NegSol wrote:I guess not everybody tests all kickstart versions all the time. Most use hdds and therefor cannot use the real old kickroms.


FWIW, though the process is a bit convoluted, you can patch 1.3 to use the A600 IDE drivers. I've done this to get a bootable 1.3 partition on MIST and MiSTer.
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Re: Minimig (Amiga) core discussion

Postby NegSol » Tue Jan 15, 2019 9:32 am

Paradroyd wrote:
NegSol wrote:I guess not everybody tests all kickstart versions all the time. Most use hdds and therefor cannot use the real old kickroms.


FWIW, though the process is a bit convoluted, you can patch 1.3 to use the A600 IDE drivers. I've done this to get a bootable 1.3 partition on MIST and MiSTer.


I did not know that. I know that my old A2000 work with an SCSI HDD with 1.3 kickrom back in the days, but that was because of the SCSI controller bios. I will have to give the patch a try someday :)

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Re: Minimig (Amiga) core discussion

Postby remowilliams » Thu Jan 17, 2019 8:56 pm

Hewhoisred wrote:I'm having some trouble with some titles when I use Minimig. Many games are affected. I used the phone to capture a sample some footage of the graphical garbage that I'm experiencing. These are WHD games using Smokemonster's/Kitrixes VHDs.


Confirmed with Banshee AGA. Issue is present in Minimig_20190112 core, but is not present in Minimig_20181208 core.

Image

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Re: Minimig (Amiga) core discussion

Postby Alynna » Fri Jan 18, 2019 12:32 am

I've started developing on the Amiga MiSTer core, as I indicated in previous posts.
I want my Amigan brothers and sisters to know, what is coming..
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Re: Minimig (Amiga) core discussion

Postby Alynna » Fri Jan 18, 2019 12:48 am

I also rewrote practically from scratch, the board autoconfig section.

Code: Select all

PROCESS (clk) BEGIN -- Autoconfig board configure section
   -- Configure new boards in this section.  Up to 7 boards supported.
   -- (Alynna rewrote this section to act more like a real Amiga Buster chip)
   -- http://amigadev.elowar.com/read/ADCD_2.1/Hardware_Manual_guide/node02C8.html
   IF sel_autoconfig='1' THEN -- Speed up everything, skip this logic if not sel_autoconfig
      CASE autoconfig_out IS
         WHEN "001" =>
            IF fastramcfg/="000" THEN
            -- Zorro II RAM (Up to 8 meg at 0x200000)
               autoconfig_data1 <= "1111";
               CASE cpuaddr(6 downto 1) IS
                  WHEN "000000" => autoconfig_data1 <= "1110";    -- Zorro-II card, add mem, no ROM
                  WHEN "000001" => --autoconfig_data1 <= "0111";   -- 4MB
                     CASE fastramcfg(1 downto 0) IS
                        WHEN "01" => autoconfig_data1 <= "0110";    -- 2MB
                        WHEN "10" => autoconfig_data1 <= "0111";    -- 4MB
                        WHEN OTHERS => autoconfig_data1 <= "0000";  -- 8MB
                     END CASE;
                  WHEN "001000" => autoconfig_data1 <= "1110";    -- Manufacturer ID: 0x139c
                  WHEN "001001" => autoconfig_data1 <= "1100";
                  WHEN "001010" => autoconfig_data1 <= "0110";
                  WHEN "001011" => autoconfig_data1 <= "0011";
                  WHEN "010011" => autoconfig_data1 <= "1110";    --serial=1
                  WHEN OTHERS => null;
               END CASE;
            END IF;
         WHEN "010" =>
            IF fastramcfg(2)='1' THEN -- Board 2
               -- Zorro III RAM (16 meg, address assigned by ROM)
               autoconfig_data2 <= "1111";
               CASE cpuaddr(6 downto 1) IS
                  WHEN "000000" => autoconfig_data2 <= "1010";    -- Zorro-III card, add mem, no ROM
                  WHEN "000001" => autoconfig_data2 <= "0000";    -- 8MB (extended to 16 in reg 08)
                  WHEN "000010" => autoconfig_data2 <= "1110";    -- ProductID=0x10 (only setting upper nibble)
                  WHEN "000100" => autoconfig_data2 <= "0000";    -- Memory card, not silenceable, Extended size (16 meg), reserved.
                  WHEN "000101" => autoconfig_data2 <= "1111";    -- 0000 - logical size matches physical size TODO change this to 0001, so it is autosized by the OS, WHEN it will be 24MB.
                  WHEN "001000" => autoconfig_data2 <= "1110";    -- Manufacturer ID: 0x139c
                  WHEN "001001" => autoconfig_data2 <= "1100";
                  WHEN "001010" => autoconfig_data2 <= "0110";
                  WHEN "001011" => autoconfig_data2 <= "0011";
                  WHEN "010011" => autoconfig_data2 <= "1101";    -- serial=2
                  WHEN OTHERS => null;
               END CASE;
            END IF;
         WHEN "011" => -- Board 3
         -- Zorro III RAM (256 meg from DDR3)
            autoconfig_data3 <= "1111";
            CASE cpuaddr(6 downto 1) IS
               WHEN "000000" => autoconfig_data3 <= "1010";    -- Zorro-III card, add mem, no ROM
               WHEN "000001" => autoconfig_data3 <= "0100";    -- 512k (extended to 256M reg 08)
               WHEN "000010" => autoconfig_data3 <= "1110";    -- ProductID=0x10 (only setting upper nibble)
               WHEN "000100" => autoconfig_data3 <= "0000";    -- Memory card, not silenceable, Extended size (256 meg), reserved.
               WHEN "000101" => autoconfig_data3 <= "1111";    -- 0000 - logical size matches physical size
               WHEN "001000" => autoconfig_data3 <= "1110";    -- Manufacturer ID: 0x139c
               WHEN "001001" => autoconfig_data3 <= "1100";
               WHEN "001010" => autoconfig_data3 <= "0110";
               WHEN "001011" => autoconfig_data3 <= "0011";
               WHEN "010011" => autoconfig_data3 <= "1111";    -- serial=3
               WHEN OTHERS => null;
            END CASE;
         WHEN OTHERS =>
            null;
      END CASE;
   END IF;   
END PROCESS;

PROCESS (clk) BEGIN -- Autoconfig action section
   IF rising_edge(clk) THEN
      IF reset='0' THEN
         autoconfig_out <= "001"; -- autoconfig on - Board 1.  Modified to support 7 boards
         turbochip_ena <= '0';      -- disable turbo_chipram until we know kickstart's running...
         z2ram_ena <='0';
         z3ram_ena <='0';
         z3ram_base<=X"01";
         z3xram_ena <='0';
         z3xram_base<=X"10";
      ELSIF enaWRreg='1' THEN
         IF sel_autoconfig='1' AND state="11" AND uds_in='0' AND clkena='1' AND autoconfig_out/="000" THEN
            CASE cpuaddr(6 downto 1) IS
               ---- Some docs here.   When adding a Z2 board you MUST configure and increment the board in
               ---- register 48.  If its a Z2 board it will NOT attempt to read register 44.  In general you
               ---- should only add new Z3 boards.
               WHEN "100100" => -- Register 0x48 - config Z2 board
                  -- All boards should be declared in this register but Z3 boards should configure in 0x44
                  -- Also declare in order.
                  CASE autoconfig_out IS
                  -- Board 1 - Z2 SDRAM
                     WHEN "001" =>
                        IF fastramcfg/="000" THEN z2ram_ena <= '1'; END IF;
                        autoconfig_out <= autoconfig_out + 1;
                     WHEN "010" => null; -- Do not increment board # for Z3 boards,
                     WHEN "011" => null; -- must be done in register 0x44.
                     WHEN OTHERS => autoconfig_out <= autoconfig_out + 1;
                  END CASE;
               ---- When adding a Z3 board you MUST configure and increment the board in register 44.
               ---- Z3 boards will access register 48 but not be configured until register 44 is hit.
               ---- You will receive a location that your board is being moved to.  Store it.
               WHEN "100010" =>    -- Register 0x44, config z3 board data area
                  CASE autoconfig_out IS
                  -- Board 2 - Z3 SDRAM
                     WHEN "010" => IF fastramcfg(2)='1' THEN z3ram_ena <= '1'; z3ram_base<=data_write(15 downto 8); END IF;
                  -- Board 3 - Z3 DDR3
                     WHEN "011" => z3xram_ena <= '1'; z3xram_base<=data_write(15 downto 8);
                  -- Board 4 - RTG
                  -- Board 5 - SANA2
                  -- Board 6 - AHI
                  -- Board 7 - Empty
                     WHEN OTHERS => null;
                  END CASE;
                  autoconfig_out <= autoconfig_out + 1;
               WHEN others =>
                  null;
            END CASE;
         END IF;
      ELSE
         IF sel_autoconfig='1' THEN
            -- IF autoconfig_out="100" THEN autoconfig_out<="000"; END IF; -- Update for number of boards + 1
            IF autoconfig_out="100" THEN turbochip_ena <= '1'; END IF; -- enable turbo_chipram after autoconfig has been done...
         END IF;
      END IF;
   END IF;   
END PROCESS;


I also adjusted the clocks, I can get a stable build about 80% of the time. I am not changing seeds. Just for my information, how do you change the seed?

pll_0002.v

Code: Select all

      .fractional_vco_multiplier("true"),
      .reference_clock_frequency("50.0 MHz"),
      .operation_mode("direct"),
      .number_of_clocks(3),
      .output_clock_frequency0("114.54544 MHz"),
      .phase_shift0("0 ps"),
      .duty_cycle0(50),
      .output_clock_frequency1("114.54544 MHz"),
      .phase_shift1("-4583 ps"),
      .duty_cycle1(50),
      .output_clock_frequency2("28.63636 MHz"),
      .phase_shift2("0 ps"),
      .duty_cycle2(50),

These clocks are based on the 14.31818mhz crystal driving the main clock of every Amiga (x2 for the main clock, x8 for the SDRAM clock)

There are more changes in TG68k.VHD than listed here, but the 256mb board is not complete yet (just the board and addressing mechanism exist right now, I still need to hook actual DDR3 up to it).

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Re: Minimig (Amiga) core discussion

Postby Sorgelig » Fri Jan 18, 2019 1:48 am

Wonderful!
Is there a repository to track your changes/progress?

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Re: Minimig (Amiga) core discussion

Postby Sorgelig » Fri Jan 18, 2019 1:52 am

Alynna wrote:Just for my information, how do you change the seed?

go to menu: Assignments -> Settings -> Compiler Settings -> Advanced Settings (Fitter). There you will find the seed value. Reset it to 1 since now it's stable.

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Re: Minimig (Amiga) core discussion

Postby Sorgelig » Fri Jan 18, 2019 2:02 am

If performance of DDR3 as Fast RAM will be at least not worse than SDR SDRAM, then it's better to remove that 16MB Fast RAM board and leave SDRAM for Chip RAM only. It will help the performance optimization and decouple CPU from chipset when it doesn't use Chip RAM.

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Re: Minimig (Amiga) core discussion

Postby Alynna » Fri Jan 18, 2019 2:26 am

https://github.com/alynna/Minimig-AGA_MiSTer

https://github.com/alynna/Minimig-AGA_M ... ngePlan.md

I'm going to try to rebuild with seed 1, and see if its still OK.

I may also find out what happens with "Performance - Aggressive 8)"

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Re: Minimig (Amiga) core discussion

Postby Alynna » Fri Jan 18, 2019 2:57 am

1 produced an unstable build. BUT! I will run the design space explorer overnight and find us a great seed.

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Re: Minimig (Amiga) core discussion

Postby Alynna » Fri Jan 18, 2019 3:40 am

I just committed all my source changes to my repo if you want to look at them.
that Minimig.rbf core is functional but do NOT use it for anything important yet. the 256MB expansion right now is just a 512K ringbuffer at 1F80000 and memory WILL start to corrupt at the 23.5mb SDRAM mark.

The next phase of this project is to map the expansion to the DDR3 ram as soon as I either select or write a DDR3 controller. That's honestly the easy part at this point.

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Re: Minimig (Amiga) core discussion

Postby Sorgelig » Fri Jan 18, 2019 4:18 am

Alynna wrote:1 produced an unstable build. BUT! I will run the design space explorer overnight and find us a great seed.

This is in vain.
Any change in the code will completely change the placement. You cannot find good seed once and forever.
Minimig needs some improvements in the code to make it stable. Probably it's the first thing need to be done before you will expand the core. Otherwise you will find yourself in endless compilation rounds after each change.

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Re: Minimig (Amiga) core discussion

Postby Alynna » Fri Jan 18, 2019 3:30 pm

so far my experience is that I have had a bad build about 1 out of every 4 tries, but the differences I can see are these:
1) I'm using quatrus 18.1 lite
2) I am using 14.31818mhz synced clocks

I am now using seed 47 but I also understand what you are talking about that being a moving target. You should try my clocks to see if it helps tho.
After I get the 256m RAM board done i'll start looking at potential code optimizations. What kind of optimizations would help the most?

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Re: Minimig (Amiga) core discussion

Postby Sorgelig » Sat Jan 19, 2019 11:41 am

Alynna wrote:These clocks are based on the 14.31818mhz crystal driving the main clock of every Amiga (x2 for the main clock, x8 for the SDRAM clock)

It absolutely doesn't matter if 14.31818 or 14.34375 like it was. The only matter is relation between SDRAM and this clock. It's the same in both cases.
So, probably you already know this has no relation to stability. The first stable build you got is just a lucky draw of exactly current source code.
Change something - and you may get unstable build :)

The main source of instability, is multiple clocks. Although SDRAM is 4x of 28MHz clock, in terms of clock networks these 2 clocks are not in sync. Each clock travels on its own clock network and get different delays on different places of FPGA. Quartus tries to guess on which places these clocks should match, but it's not always obvious. Hence we have metastability when different builds behave differently.
Even though you may think that current build is stable, the instability can hide in some places you didn't check yet. Some games may have garbage on screen or don't run at all.

The "cheaper" solution is to use a single clock 114MHz. Use clock enable for 28MHz, so everything will be on the same clock network. Of course code must be revised to make sure these is no use of falling edge of 28MHz clock or other tricks working on clock and not working on clock enable. Another problem may arise is how the whole project will work on 114MHz clock.

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Re: Minimig (Amiga) core discussion

Postby Alynna » Sat Jan 19, 2019 12:31 pm

so heres a question, is it possible to create a 114mhz clock from the 28mhz clock by multiplying it by 4? Then we'll just have the 28mhz clock and everything will be in sync. Because I am sure there are plenty of rising/falling edge tricks being played, but down at 7mhz which is being derived by the 28mhz clock.

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Re: Minimig (Amiga) core discussion

Postby Sorgelig » Sat Jan 19, 2019 1:11 pm

Nope. How you imagine the clock multiplication? This is against the physics. PLL is used for multiplication but it's virtual multiplication. Actually it's still division of much higher clock.
You can use PLL to make 114 from 28, but it will be even worse than current case. The only way to simplify the clocks is use 114MHz for the whole project.
Alternative possible solution to isolate 114MHz code from 28MHz code as much as possible with less possible connections.
Currently i see 114MHz "travels" to TG68K which is not a good thing. CPU doesn't work on 114MHz, so it's better to remove this clock from CPU. So, by locating 114MHz only around SDRAM the instability will have less chance from my point of view.

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Re: Minimig (Amiga) core discussion

Postby Alynna » Sat Jan 19, 2019 1:37 pm

Sorgelig wrote:Nope. How you imagine the clock multiplication? This is against the physics. PLL is used for multiplication but it's virtual multiplication. Actually it's still division of much higher clock.
You can use PLL to make 114 from 28, but it will be even worse than current case. The only way to simplify the clocks is use 114MHz for the whole project.
Alternative possible solution to isolate 114MHz code from 28MHz code as much as possible with less possible connections.
Currently i see 114MHz "travels" to TG68K which is not a good thing. CPU doesn't work on 114MHz, so it's better to remove this clock from CPU. So, by locating 114MHz only around SDRAM the instability will have less chance from my point of view.


Actually never mind the above post.
I have removed the 28mhz clock, only the sdram_ctrl and sdram clock are there now.
I made a clock quarterer and deriving the 28mhz clock directly from the SDRAM clock.

Code: Select all

// 28mhz
reg clk_56_r;
reg clk_28_r;
always @(posedge clk_114)
begin
   if (~rst) begin
      clk_56_r <= 1'b0;
      clk_28_r <= 1'b0;
   end else begin
      clk_56_r <= ~clk_56_r;
      if (~clk_56_r) clk_28_r <= ~clk_28_r;   
   end
end
assign clk_28 = clk_28_r;

I'll tell you what comes of it in 20 mins.

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Re: Minimig (Amiga) core discussion

Postby Sorgelig » Sat Jan 19, 2019 1:55 pm

You've made things only worse.
The clocks you've created are called asynchronous clocks. This is worst thing you can do for clocks :)
You will see Quartus warnings about signals used as clocks without declaration.
You may describe these clocks in SDC file, so Quartus won't complain. But it is great source of instabilities.


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