Arduino MKR Vidor 4000

[olin]

This new board from Arduino seems like an interesting toy. It's a combination of ARM Cortex M0 and FPGA Intel (Altera) Cyclone 10CL016 (16K LE) with 8MB of SDRAM and Micro HDMI port on a small board, plus pins to connect peripherals (SD card and joysticks - possibly NES style
could be used as they require only 3 data lines, see uzebox project for reference). The price also seems to be reasonable (50Eur).
I wonder whether a mini version of MiST could be be achieved, sporting some smaller cores, 8 bit micros and old arcades.

[Sorgelig]

This was my thought when i've saw the news back in the May. I even bought it. Unfortunately i have not enough time to start. In theory it's possible to make a mini MiST-like device.
It's good that developers was thinking about core loading from MCU, so they have connected JTAG pins to MCU. I don't know if Cyclone 10 differs from Cynclon II-V so much. If no, then they did it wrong way. They should connect PS pins to MCU instead of JTAG for core uploading. Probably, they thought they could implement USB Blaster in MCU so users won't need to buy a separate USB Blaster. I doubt they can achieve this because i've tried one sample project which has core inside the MCU firmware and push it to FPGA at start. It took me some time to realize that core uploading takes forever. I've disconnected it several times and reset thinking it doesn't work. But it tuned out i need to wait around 1 minute(!!!) before it start to output the video to HDMI.
They use bit banging for JTAG interface - that's why it's extremely slow to upload the core. I don't think they will be able to implement reliable USB Blaster through such slow communication. Not sure if it can be improved - there is no much room in improvement of bit-bang SPI. I have no idea why they didn't connect standard SPI of MCU for JTAG. May be JTAG interface is different from SPI, or may be they simply didn't think about it. If they would connect PS to SPI like it's done on MiST, then it would be fast.
According to schematic hardware SPI on MCU has connection to FPGA, so at least communication with FPGA can be fast.

There are several things make me a little worry about possibility to port some subset of MiST:
1) MCU has only 32KB or RAM instead of 64KB on MiST. Probably, after throwing away core-specific support for ST, Minimig, Archie - it will fit. Though i wouldn't like to throw away the Minimig.
2) USB support code may leave less free space for code and data, so see (1)
3) HDMI output requires well formed specific resolutions and will require some kind of scaler and frame converter. It may occupy large part of FPGA and there is no second high-speed RAM (like DDR3 on MiSTer) available for fullframe operations.
It's of course possible to connect VGA output through PCIe connector, or even use miniHDMI with external simple 2bits per color VGA adapter. First solution will require a special addon PCB which will render solution to not so attractive as originally looked. Second solution will limit VGA colors.

Overall, it can be a good challenge, although it's not as promising as it looked at first.

[olin]

Excellent analysis - it has more information than I expected.

According to schematic hardware SPI on MCU has connection to FPGA, so at least communication with FPGA can be fast.

The board has a Flash memory connected to the FPGA. I wonder whether some sort of 'FPGA bootloader' could be designed that would run on FPGA fabric and would:
1) receive bitstream data over HW SPI from the MCU to the FPGA
2) store the bitstream to Serial Flash
3) do a soft reboot to force FPGA to load the stored bitstream from flash. Maybe the reboot could be done from MCU.

Of course the first installation would require to bitbang the 'FPGA bootloader' into the FPGA over the slow connection. Each core would need to include such bitstream loader (to allow loading different cores), but hopefully this would not occupy too many LE. It's just a thought, maybe this can not be done, or would be inefficient and slow as well.

[Sorgelig]

It's hard to tell at this stage.
Need to experiment. May be bitbanging can be improved with assembler function using minimal instructions.
this is demo i was talking about: https://github.com/Giako68/TEXT_DEMO

You may start to explore it to check for possible improvements of JTAG uploading. Don't even need to change the core for this experiment.

Using EEPROM for each core loading isn't a good way as it will wear out - it's not supposed to be used this way.

[olin]

Using EEPROM for each core loading isn't a good way as it will wear out - it's not supposed to be used this way.

It's a valid concern. I checked the part datasheet (W25Q16DV) which specifies "More than 100,000 erase/program cycles". If I calculate that in average I will erase the flash 1590x per year (3 days a week * 53 weeks in year * 10 core changes per day) the flash memory should last me around 62 years. Every person is different and may change cores more often or play more times a week, still I'd guess in average it should last at least 20+ years.

[Sorgelig]

This is not the main concern. Need to check which cores can fit, and if MiST firmware will fit. FPGA is actually smaller than on MiST, so can't expect much.

[uigiflip]

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[uigiflip]

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