MarkP wrote:I'm not sure if I'm reading it right, but does the shift matrix diagram (including that brilliant but kooky 2-bit-per-cell design that rolls the FIFO/IR into the shiftreg/RR) imply that it loads in 4 words just-in-time (except in the case of the every-16-pixels glitch) for the previous 4 to have run out in low rez, shunts them all down / shifts out the first pixel / starts loading the first word of the next block of four in more or less the one motion, and places four bits off the far right end of what are effectively 4 parallel, single tapped, 1-bit shift regs with each shift...?
To be honest, I'm not 100% sure I understand exactly everything in that very long sentence
, but mostly yes. That's how hardware works, in parallel. There is no "penalty" or "risk" for doing things in the precise last cycle. Actually it is harder and more expensive (requires more transistors) to do it otherwise.
And for medium it only loads in two words at a time, twice as often because the individual bits in each effectively-parallel-1-bit reg are then shifted out at twice the frequency, with the lower 2 bits then always being zero so only 4 colours can be produced despite 4 bits technically being shifted out... and for hi-rez it only loads in a single word, and performs the internal transfer 4x as often as in low rez, with only the uppermost output ever changing?
The transfer from the FIFO/IR to the RR registers is always 4 words (64 bits), always after every 4 LOAD pulses, regardless of the resolution. What happens is that depending on the resolution the output of one shift register is connected to the input of the other (see the overall shift logic diagram at that same post with the shift matrix). So, for instance in high rez, the four shift registers are combined in a single 64-bit shift. So the unused output bits on the higher resolutions might be not zero, but they are masked out later by the palette lookup logic, and the monochrome output obviously uses a single bit. That reminds me that I still didn't post schematics of that later stages of the video output, sorry about that.
Versus the old model I remember seeing drawn up in the past where the IR and RR are separate 1-bit deep ...
I don't have right now the pictures of Alien's famous articles, but I believe he got the model mostly right in this regard. Combining 1 bit of IR and RR in a single cell is just a physical organization. Logically it behaves exactly the same as it were separate.