Congratulations on initiating some improvements needed to get closer to a real C64.
I hope to be able to help in the development of these improvements (but I have no knowledge of VHDL or Verilog).
I am not a guru, but I can help you with hardware.
How can I download the beta ??
On the other hand, the JiffyDOS not have problem .... Taps and Jiffy are not compatible either in the real machine (the part of the rom that handles the tape routines is replaced by the acceleration routines), so it Logic is to use the standard rom or Jiffy as before.
Electronically Tape Port:
read pin is connected to pin |FLAG (note 1) of CIA 1 (DC00 to DCFF) (Input).
write pin is connected to pin P3 (of CPU) (output) (need for implement?).
CASS motor is connected to pin P5 (of CPU) and is used to start/stop/continue the .Tap decoder (output).
CASS sense is connected to pin P4 (of CPU) and is used to detect any key pressed on tape deck (it must be ever active(low?) on TAP decoder)
+5V not used on Implemented system
GND not used on implemented system
Note 1: |FLAG pin is implemented on FPGA64 from v0.18 (CIA has flag_n input).
I Maybe it should be inverted and synchronized with the system clock (attention to this).http://www.zimmers.net/anonftp/pub/cbm/ ... tte-io.gif
very explanatory links about the .Tap format of C64 and as this works with tapes (They explain it better than me).
At hardware level, I wait for your doubts or comments. I hope to help you.http://c64tapes.org/dokuwiki/doku.php?i ... ng_loadershttp://unusedino.de/ec64/technical/formats/tap.htmlhttp://www.zimmers.net/anonftp/pub/cbm/ ... aticP2.png
Hope this information is helpful.
Very Thanks again.