Steven Seagal wrote: You need "round cycles up to 4" only for RAM and Shifter accesses.
Funny but this was already in the Engineering Hardware Specification of 1986:
See how the Memory controller (MMU) sits between the CPU and the RAM/Shifter?
In the schema above, there's also "Buffers" near the Shifter, don't know what it is.
The scheme is a bit misleading. MMU doesn't really sit between the CPU and RAM, those buffers are.
There are two data buses in the ST, the main CPU bus, and the RAM/SHIFTER (and nothing else) bus. Four TTL chips (two buffers and two latches) connect or separate both buses. MMU is connected to the main data bus. But it controls the buffers and the RAM address bus.
Where "is" $ffff8260?
Yes. It lives in both chips, GLUE and SHIFTER. You can say it is actually a SHIFTER register, only shadowed by GLUE. Reads are performed from SHIFTER, not from GLUE.
troed wrote:... GLUE can definitely detect manipulation of it with 2 cycle accuracy
Actually within a single cycle accuracy, not two
Steven Seagal wrote:But obviously, shift mode and HSCROLL are in the Shifter, with maybe only a bit for each in the GLUE (on/off).
Don't know about HSCROLL, but GLUE shadows BOTH
bits of Rez (Shift Mode). You'll wonder why? Why it cares exactly about which color resolution is currently selected, low or med. After all GLUE only cares about frequency, not about resolution ... Well, there is a reason most wouldn't expect ... let's make it a mini quiz of it.