Processor comparisons

[Zarchos]

One question: is that old basic architecture and command set of ARM what is base for nowadays, widely used, multi core CPUs - used in smartphones, Raspberry Pi, etc. I had some 600 MHz ARM, manufactured by Intel in palmtop, some 10 years ago.

From latest comments of Sophie Wilson, who created the ARM instructions set : yes.
Meaning : with very minor modifications old code running on the Archies run on the latest ARM chips.

[AtariZoll]

Well, in that case I don't see the point of discussions 68K vs. ARM. One is history, retro, other is still developing. Wait, people who works on that Amiga GHz 68000 based beast will not agree ... Ah, I even don't remember how they named it

[Zarchos]

Well, in that case I don't see the point of discussions 68K vs. ARM. One is history, retro, other is still developing. Wait, people who works on that Amiga GHz 68000 based beast will not agree ... Ah, I even don't remember how they named it

???
I need my litre of coffee, I really don't understand your reasonning at all.
We are of course speaking of what was available back in the days.

[AtariZoll]

The reasoning is simple - the better survived
OK, I read it little. But found strange to come with things that ARM has no divide instruction, for instance. It was RISC, so I see it as normal.
All I remember from times when Archimedes arrived on market was praising and euphoria in magazines. Ah sorry, this is processor comparison thread.
What I would like to see is some speed test of Texas Instruments TI 9900 - it was one of the first 16-bit CPUs, and in fact total opposite concept than RISC.

[simonsunnyboy]

Yes, the ancestor of all modern ARM IP cores.

[simonsunnyboy]

Acorn Risc Machine in the beginning, someway around 92 or 93 (Zarchos, correct me), it was renamed to Advanced RISC Machine.

[Zarchos]

Acorn Risc Machine in the beginning, someway around 92 or 93 (Zarchos, correct me), it was renamed to Advanced RISC Machine.

1st ARM1 (working prototype from day 1) working in 1985, available as an add-on and development expansion for the Acorn 8 bits machines, and also as the CPU for standalone Archimedes prototype named A500, for developpers.
Probably the machine Lander and Zarch were developped on (and the ARM1 has no multiplication opcodes. So : no division, and no multiplication instructions are used in these games).

1st Archimedes commercially launched with ARM2 (still no division instruction, but 2 multiplication instructions now implemented) 8 Mhz June 1987. Happy birthday btw.

ARM1 : 25 000 transistors.
ARM2 : 30 000 transistors.

[simonsunnyboy]

No horizontal blank interrupt? And I remember so many great demos on the A3000 with raster bars.....Brothers In Arm come to mind *oh the memories*

Back to the Archie, I think it could have been Armaxess as well. My supply on Archie demos was limited, I never got more than what my brother bought through a PD library in 1991/92.

I am so sad I didn't backup my Archie productions made with BBC BASIC .... the machine is still on the roof my parent's house. The NEC monitor is dead and so are the floppiiess. We had an A3000 with 2MB and RISC OS 3.1 btw.

[Frank B]

You know I agree : the RISC philosophy has its weaknesses / drawbacks.
Can you please give an example of the bits extracting instructions (and what they do exactly, I do not remember well enough the bits of 68000 ASM I had try to learn several decades ago), and the number of cycles used ?
Your quote :
' Compare the flexibility of the bitfield instructions on the 020 to anything in the ARM. There's no equivalent to bitfield insert or bitfield extract instructions on the ARM. How many 32 bit (!) instructions would be needed to do the equivalent on ARM?
'
Then I'll try to tell you how it could be performed on the ARM chip.
There is a hidden feature of the LDR (load register) instruction, not detailed in the 2 books about ARM programming, but clearly detailed in the ARM VLSI Data Manual.
I make heavy use of this feature in all my graphical routines.
And if all this is beginning to be off-topic, please complain gently and not with harsh phrasing : the teacher/student behaviour is sthing I do not stand anymore, and I mean it has been like that for several decades. I am not sbdy's inferior, in any way.

I didn't think I was being harsh or impolite.
The RISC chips were designed for compilers. The CISC chips were designed to be usable for human assembler coders.
Here's some detail on the bitfield instructions http://68k.hax.com/BFINS
They're really nice. I remember another thing which was odd about the ARM. The status register bits in the program counter register.
26 bit addressing must have hurt the platform for years.

[Zarchos]

[SNIP]

And if all this is beginning to be off-topic, please complain gently and not with harsh phrasing : the teacher/student behaviour is sthing I do not stand anymore, and I mean it has been like that for several decades. I am not sbdy's inferior, in any way.

I didn't think I was being harsh or impolite.
The RISC chips were designed for compilers. The CISC chips were designed to be usable for human assembler coders.
Here's some detail on the bitfield instructions http://68k.hax.com/BFINS
They're really nice. I remember another thing which was odd about the ARM. The status register bits in the program counter register.
26 bit addressing must have hurt the platform for years.

You were not : my remark was self-criticism, for everybody, not aimed at you

I don't think the RISC chips were designed for compilers and the CISC chips for humans to be able to program in assembler.
I would say exactly the opposite.
At least for the ARM chips.
Ask people who had an Archie : it is for many of them the machine they started to learn assembly language with.
People coming from the ST or the QL all agreed it was easier to use ASM on the Archie.
I think people make a big mistake about this RISC thing, because there is Reduced in the acronym.
The truth is here, listen :
https://youtu.be/Rc5i6tA3dH0?t=4m14s
and the ARM chip is the example of a RISC chip, but not strongly RISC : their designers, coming from the 6502, wanted to keep some of the good sides of this chip.
I think people could have a quick look at this :
http://www.peter-cockerell.net/aalp/
it is the online best book about programming the ARM2 on the Archie.

Oh and yes you are right about the status register bits in the PC, it has hurt and made things difficult when this has been changed.

For the bitfield instructions, that looks very complex to me ; I need an example with what it does in plain, understandable English, sorry

[Frank B]

I don't think the RISC chips were designed for compilers and the CISC chips for humans to be able to program in assembler.
I would say exactly the opposite.
At least for the ARM chips.

For the bitfield instructions, that looks very complex to me ; I need an example with what it does in plain, understandable English, sorry

A bitfield insert instruction takes an arbitrary sized binary value and inserts it into an arbitrary bit shifted position in a destination operand.
A bitfield extract instruction does the opposite. It was designed to access c structures which use packed bits.

Say you had a 4 bit packed pixel format which looks like this 3210 3210 3210 3210.
You could set any pixel value in a single instruction.

There is no need to do the following steps
1) read whole 16 bit value into a register.
2) buffer it to another register (you'll need it later)
3) shift left to align the nibble you want in the lower four bits
4) mask off unwanted nibbles
5) zero another register
6) or the contents from step 3 to it
7) mask off all bits from the buffered register.
shift it as appropriate
9) combine them
10) write the new value back to memory

It does all that in a *single* instruction. It isn't limited to any length. You could set 5 bits or 6 etc etc.

At least the ARM doesn't contain truly horrible stuff like software pipeline hazards or branch delay slots (shudder). Some RISC architectures do.

I have a hazy memory the PC address can't be relied upon though. Is it out by 3 instructions worth due to the 3 stage pipeline?

Well you probably wouldn't need to shift depending on what you wanted to do, but you get the gist I hope
It's like a software blitter.

My assembler background is the 680x0 and the 6502/65816.

I did a couple of ARM courses for a past employer. It was some time ago.
The courses were run by the guy that wrote the RISCOS font renderer oddly enough

[Zarchos]

I'll answer tomorrow morning but I think there is no need of 10 steps ... thanks to the power of the barrel shifter applied to the 3rd operand (with a constant it costs 0 extra cycle, 1 if it is a register)
Yes most intructions have 3 operands, and the barrel shifter alters the content of the last one, remember ?
I'd say all in all it would take 20 cycles of 125 ns each on an ARM2 machine at 8 Mhz.
How many on your target machines ?

The PC (that is R15), in User Mode, always points to address of current instruction executing + 8 bytes.
Which turns out not to be an issue.
When you do the equivalent of a GO SUB, the right value to return from your sub procedure is placed into R14, so you write MOV PC,R14 at the end of your sub procedure (called with BL (Branch with Link)) and that is it.

[Frank B]

I'll answer tomorrow morning but I think there is no need of 10 steps ... thanks to the power of the barrel shifter applied to the 3rd operand (with a constant it costs 0 extra cycle, 1 if it is a register)
Yes most intructions have 3 operands, and the barrel shifter alters the content of the last one, remember ?
I'd say all in all it would take 20 cycles of 125 ns each on an ARM2 machine at 8 Mhz.
How many on your target machines ?

The PC (that is R15), in User Mode, always points to address of current instruction executing + 8 bytes.
Which turns out not to be an issue.
When you do the equivalent of a GO SUB, the right value to return from your sub procedure is placed into R14, so you write MOV PC,R14 at the end of your sub procedure (called with BL (Branch with Link)) and that is it.

I'd be interested in seeing how dense the code is. I think the 68020 will win here.
For C code which is APCS I'd imagine you also have the overhead of function prologue and epilogue. Ie setting up your frame pointer. Your MOV PC,R14 is 4 bytes. An RTS is 2 bytes on the 68k. Half the size. The 020 also has instructions for storing the stack in another register and offsetting it for local storage space. link and unlink if memory serves. All programmer conveniences. Does the arm32 ISA have atomic instructions for synchronisation?
How well does the 12 mhz ARM2 compare to say the 040 at 25 mhz? They're roughly the same age.

ARM32 was reasonably fast but it wasn't competitive for code density. That's why ARM introduced thumb mode.
The ISA is a bit messy now. You have ARM32, Thumb, Thumb 2 and arm64. ARM64 looks nothing like arm32.

Frank

[Zarchos]

ARM2 has no instruction, uninterruptible, to do synchronisation (you are speaking about an instruction allowing to easily implement semaphores, right ?)
But it is available from the ARM3, and then in the ARM250.
It is why I 'fight' when people say the CPU inside an ARM250 is an ARM2 : it is not.
The ARM250 CPU is an ARM3 without the cache the ARM3 has.

For speed comparison, I have read the ARM250 (with its 7.x MIPS) is often compared to a 68040 at 20/25 Mhz.
Honestly I doubt it.
It is again this 'MIPS thing' that is just not right enough to be used to benchmark the CPUs.

And yes you are perfectly right : for code density I bet the ARM loses.
But, honestly, you chose an ultra specialised instruction ... in so many other cases, it is the ARM that wins.(typical IF THEN ELSE ELSIF with all instructions which can be conditional).
In use, if you see the size the Archie games / demos / apps take, it is always a bit more than on other machines because of the graphics using 8 bits per pixel ...
I don't see any 'advanced' programs needing more than 2 Mbytes to run, and 50% run with 1 Mbyte.

[Frank B]

ARM2 has no instruction, uninterruptible, to do synchronisation (you are speaking about an instruction allowing to easily implement semaphores, right ?)
But it is available from the ARM3, and then in the ARM250.
It is why I 'fight' when people say the CPU inside an ARM250 is an ARM2 : it is not.
The ARM250 CPU is an ARM3 without the cache the ARM3 has.

For speed comparison, I have read the ARM250 (with its 7.x MIPS) is often compared to a 68040 at 20/25 Mhz.
Honestly I doubt it.
It is again this 'MIPS thing' that is just not right enough to be used to benchmark the CPUs.

Yes. I'm talking about thread synchronisation. The 68000 from 78 had TAS for that specific purpose. Just don't try to use it on the Amiga
The 040 executes most instructions in a single cycle. It's addressing modes are more comprehensive. It has more registers too
It doesn't sacrifice general purpose registers to the PC or LR for example.

I liked the three operands and i liked the arbitrary shift but the addressing modes are too restrictive. Down side to a load store arch.
Give me an 040/060 with its instruction set any day.

Code density does matter. It has implications for the instruction cache for example. Look up some of the 68k addressing modes. They're insanely powerful. You can do memory pointer indirect without even *using* a register on the 020.

The ARM lacks support for some useful stuff like BCD. The 6502 supports that. It's ultra useful for game high scores when you have no divide instruction

[Zarchos]

ARM2 has no instruction, uninterruptible, to do synchronisation (you are speaking about an instruction allowing to easily implement semaphores, right ?)
But it is available from the ARM3, and then in the ARM250.
It is why I 'fight' when people say the CPU inside an ARM250 is an ARM2 : it is not.
The ARM250 CPU is an ARM3 without the cache the ARM3 has.

For speed comparison, I have read the ARM250 (with its 7.x MIPS) is often compared to a 68040 at 20/25 Mhz.
Honestly I doubt it.
It is again this 'MIPS thing' that is just not right enough to be used to benchmark the CPUs.

Yes. I'm talking about thread synchronisation. The 68000 from 78 had TAS for that specific purpose. Just don't try to use it on the Amiga
The 040 executes most instructions in a single cycle. It's addressing modes are more comprehensive. It has more registers too
It doesn't sacrifice general purpose registers to the PC or LR for example.

I liked the three operands and i liked the arbitrary shift but the addressing modes are too restrictive. Down side to a load store arch.
Give me an 040/060 with its instruction set any day.

LR is not sacrificed
In your subprocedure if you really need it you can store it somewhere and load it back directly into the PC when you want to come back to the callant..
90% of the time you have enough registers available to not need R14 in your subprocedure code ...

Why is TAS not usable on the Amiga ?
Because of the DMA oriented architecture ?

[Frank B]

Why is TAS not usable on the Amiga ?
Because of the DMA oriented architecture ?

Yes. It can clash with the DMA on 68k machines. The result is a black screen and lots of buzzing noises.

[Zarchos]

Why is TAS not usable on the Amiga ?
Because of the DMA oriented architecture ?

Yes. It can clash with the DMA on 68k machines. The result is a black screen and lots of buzzing noises.

Sound and picture with a Guru flashing the Amiga was the 1st multimedia machine, for sure

[Frank B]

Yes. It can clash with the DMA on 68k machines. The result is a black screen and lots of buzzing noises.

Sound and picture with a Guru flashing the Amiga was the 1st multimedia machine, for sure

Oh no. It's worse than that. It literally fuxxors the display. The whole machine falls over and needs power cycled.

[Zarchos]

Yes. It can clash with the DMA on 68k machines. The result is a black screen and lots of buzzing noises.

Sound and picture with a Guru flashing the Amiga was the 1st multimedia machine, for sure

Oh no. It's worse than that. It literally fuxxors the display. The whole machine falls over and needs power cycled.

Added to my list of interesting facts about the Amiga, when I will make this video in French for the people on the Gamopat forum who took the piss of me.
If you have more funny little things to say, please pm me a list.
I'm serious, I'd be grateful.

[Frank B]

I'd just leave the Amiga fan bois to it. No use interacting with nutters.

[Zarchos]

The ARM lacks support for some useful stuff like BCD. The 6502 supports that. It's ultra useful for game high scores when you have no divide instruction

I think there some clever algos listed in the ARM VLSI manual to do exactly that (BCD) ... I'll list that here.
Same thing to divide by any value ... more instructions but it'll be interesting to compare with the number of cycles it takes on the 68000.
And well as you very well know, a divide is nothing more than a multiply x 1/value ; and because all ARM registers are 32 bits, with fixed point arithmetic the ARM can do great and be precise
See for everything 3D on the Archie, it is not an issue.(ok chunky graphics modes do help a lot).
https://www.chiark.greenend.org.uk/~the ... l-VLSI.pdf page 3-41

BCD, from Acorn Google Group programmer :
> *However*, if you insist: one thing worth knowing is that division
> by a fixed constant (10, for instance) can be coded much more efficiently
> than general-purpose division. Here's how to do it for division by 10;
> it may be possible to shave a few cycles off this.
It is possible.

> ; r0 contains any 32-bit unsigned integer
SUB r2, r0, r0, LSR#2 ; r0-(r0/4)

> ADD r2, r2, r2, LSR#4 ; * (1+1/16)
> ADD r2, r2, r2, LSR#8 ; * (1+1/256)
> ADD r2, r2, r2, LSR#16 ; * (1+1/65536)
> ; we have now, more or less, multiplied by 8/5
> MOV r2, r2, r2, LSR#3
> ; so now r2 is at most r0/10, and [...] at least r0/10-1.51.

> ADD r1, r2, r2, LSL#2 ; 5*r2
SUBS r1, r0, r1, LSL#1 ; r0 - 10*r2
SUBMI r2, r2, #1
ADDMI r1, r1, #10

> CMP r1, #10
> SUBGE r1, r1, #10
> ADDGE r2, r2, #1
> ; now r2,r1 contain the quotient and remainder on dividing the
> ; original contents of r0 by 10
> ; and r0 is preserved

That's 12 cycles

[wongck]

Very technical now.
But the bottom line is that
I can play Wing Commander on an Intel 286 computer and while we are stuck on Elite.

[Zarchos]

Very technical now.
But the bottom line is that
I can play Wing Commander on an Intel 286 computer and while we are stuck on Elite.

Ever heard of Starfighter 3000 ?
https://youtu.be/gKEaX4RjWkk

[wongck]

Ever heard of Starfighter 3000 ?
https://youtu.be/gKEaX4RjWkk

No... where to find for Atari falcon ?