Frank B wrote:
The ARM lacks support for some useful stuff like BCD. The 6502 supports that. It's ultra useful for game high scores when you have no divide instruction
I think there some clever algos listed in the ARM VLSI manual to do exactly that (BCD) ... I'll list that here.
Same thing to divide by any value ... more instructions but it'll be interesting to compare with the number of cycles it takes on the 68000.
And well as you very well know, a divide is nothing more than a multiply x 1/value ; and because all ARM registers are 32 bits, with fixed point arithmetic the ARM can do great and be precise
See for everything 3D on the Archie, it is not an issue.(ok chunky graphics modes do help a lot). https://www.chiark.greenend.org.uk/~the ... l-VLSI.pdf
BCD, from Acorn Google Group programmer :
> *However*, if you insist: one thing worth knowing is that division
> by a fixed constant (10, for instance) can be coded much more efficiently
> than general-purpose division. Here's how to do it for division by 10;
> it may be possible to shave a few cycles off this.
It is possible.
> ; r0 contains any 32-bit unsigned integer
SUB r2, r0, r0, LSR#2 ; r0-(r0/4)
> ADD r2, r2, r2, LSR#4 ; * (1+1/16)
> ADD r2, r2, r2, LSR#8 ; * (1+1/256)
> ADD r2, r2, r2, LSR#16 ; * (1+1/65536)
> ; we have now, more or less, multiplied by 8/5
> MOV r2, r2, r2, LSR#3
> ; so now r2 is at most r0/10, and [...] at least r0/10-1.51.
> ADD r1, r2, r2, LSL#2 ; 5*r2
SUBS r1, r0, r1, LSL#1 ; r0 - 10*r2
SUBMI r2, r2, #1
ADDMI r1, r1, #10
> CMP r1, #10
> SUBGE r1, r1, #10
> ADDGE r2, r2, #1
> ; now r2,r1 contain the quotient and remainder on dividing the
> ; original contents of r0 by 10
> ; and r0 is preserved
That's 12 cycles
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