Cacheable areas on Falcon?

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Foxie
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Cacheable areas on Falcon?

Postby Foxie » Wed Apr 11, 2018 6:23 pm

Are the interrupt vectors cached on the Falcon (with or without CT60)? If they are, are they read from the instruction or data cache?

I need to re-program the interrupt vector to a new address each time an interrupt occurs. I don't really want to flush the cache in my interrupt handler.

Something like this:

first_isr:
move.l #second_isr,$110.w
<do stuff>
rte

second_isr:
move.l #third_isr,$110.w
<do stuff>
rte

third_isr:
move.l #fourth_isr,$110.w
<do stuff>
rte

fourth_isr:
move.l #first_isr,$110.w
<do stuff>
rte

I might also want to use self-modifying code to modify the immediate data in the four ISR routines. I'm pretty sure the Falcon needs a cache flush when I do that?

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Re: Cacheable areas on Falcon?

Postby shoggoth » Wed Apr 11, 2018 7:16 pm

Vectors themselves are data, written as data, cached as data. So no problem there.

Self modifying code - find another way.
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Re: Cacheable areas on Falcon?

Postby ggn » Thu Apr 12, 2018 7:12 am

If you specifically want to play with the interrupt vectors, a good idea might be to change the VBR and have different sets of interrupt tables ready.
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Re: Cacheable areas on Falcon?

Postby ThorstenOtto » Fri Apr 13, 2018 5:29 am

ggn wrote:If you specifically want to play with the interrupt vectors, a good idea might be to change the VBR and have different sets of interrupt tables ready.


Not really a good idea when using TOS. Not only that you would have to copy the whole memory area of vectors first (because that change applies to *all* interrupts), but there are also certain routines in TOS that don't expect the interrupt vectors suddenly being placed somewhere else, and don't look at the VBR.

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Re: Cacheable areas on Falcon?

Postby ggn » Fri Apr 13, 2018 7:40 am

ThorstenOtto wrote:Not really a good idea when using TOS. Not only that you would have to copy the whole memory area of vectors first (because that change applies to *all* interrupts),


And where's the problem with that? It's not like you need to copy around megabytes of RAM.

ThorstenOtto wrote:but there are also certain routines in TOS that don't expect the interrupt vectors suddenly being placed somewhere else, and don't look at the VBR.


That's always an issue when bending interrupt vertors - it's the programmer's responsibility. I don't see why the VBR is any more dangerous in this regard. (ok, there's the chance of other applications bending the vectors after you created a copy of the VBR but well, this all depends on what one wants to do).

Also, the OP didn't mention TOS at all, right? So why bring this up at all?
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Re: Cacheable areas on Falcon?

Postby Foxie » Fri Apr 13, 2018 6:59 pm

shoggoth wrote:Vectors themselves are data, written as data, cached as data. So no problem there.

Self modifying code - find another way.


Thanks! Wouldn't self-modifying code be OK if I just flush the cache after doing the modification? I only need to modify the code 200 times a second (although the ISR runs tens of thousands of times a second).


ggn wrote:Also, the OP didn't mention TOS at all, right? So why bring this up at all?


Unfortunately I do need to keep TOS running.

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Re: Cacheable areas on Falcon?

Postby shoggoth » Sat Apr 14, 2018 7:57 am

More details about the actual application for this code would help us give better input, methinks.
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Re: Cacheable areas on Falcon?

Postby Foxie » Sat Apr 14, 2018 5:59 pm

shoggoth wrote:More details about the actual application for this code would help us give better input, methinks.


It's a Cubase driver for the YM chip. Timer D is producing SID waveforms by adjusting YM registers at up to 10kHz. My current code reads a lookup table of waveform parameters and writes them to the chip in the ISR. It's slow because it needs to calculate and wrap the address it's reading from.

It can go much faster if I permit self-modifying code. The waveform parameters can be immediate data like this:

Code: Select all

isr1:
  move.l #$xx00xx00,$ffff8800.w
  move.l #$xx00xx00,$ffff8800.w
  move.l #$xx00xx00,$ffff8800.w
  move.l #isr2,$110.w
  move.b #$ef,$fffffa11.w
  rte

isr2:
  <as above but with different immediate data>

etc.


For flushing the cache I plan to use something like this:

Code: Select all

   move.l  d0,-(sp)
   move.w  sr,-(sp)
   move.w  #$2700,sr
   dc.w  $4e7a,$0002      ; movec cacr,d0
   tst.w  d0
   bmi.b  .higher030
   or.w  #8,d0      ; CI (instruction cache)
   dc.w  $4e7b,$0002      ; movec d0,cacr
   bra.b  .done030
.higher030:
   dc.w  $f4f8         ; cpusha both
   nop               ; Prevent parallel execution on 060.
.done030:
   move.w  (sp)+,sr
   move.l  (sp)+,d0


Unless there's a TOS routine I don't know about for flushing the cache? I hear there's a branch cache in the 060, and I'm not sure if the above routine succeeds in clearing it. The 060 manual says something like you must clear instruction and data cache before executing self-modified code.

Do you think 50 to 200 cache flushes per second would impact performance?

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Re: Cacheable areas on Falcon?

Postby mikro » Sun Apr 15, 2018 12:04 am

I don't understand why are you so concerned about EA calculation on 060. It will be a magnitude faster than your immediate EA + SMC code.

Also, if it's called only 200 times per second, how simple move.l (a0)+,$ffff8800.w can be a speed bottleneck on 030?

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Re: Cacheable areas on Falcon?

Postby Foxie » Sun Apr 15, 2018 2:06 am

mikro wrote:I don't understand why are you so concerned about EA calculation on 060. It will be a magnitude faster than your immediate EA + SMC code.

Also, if it's called only 200 times per second, how simple move.l (a0)+,$ffff8800.w can be a speed bottleneck on 030?


The code needs to run on an 8MHz 68000, so speed is very critical there. I could just have two separate routines for cached and uncached CPUs but it seems like overkill.

I only need to change the contents of the data 200 times a second. The actual ISR is running much faster, about 10kHz. With my current code, an 8MHz ST becomes very sluggish when running at 10kHz.


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