Foxie wrote:I was looking at that thread, but I'm still not completely sure. Does that mean a YM access is always exactly five 8MHz cycles on ST/TT/Falcon? And I assume on an accelerated Falcon no rounding up by four will occur?
What I'm trying to determine is how fast an I/O port pin can be toggled. I imagine if you don't have any rounding or instruction fetching overhead, the period will be about 1.25us (two accesses of five 8 MHz cycles).
ijor wrote:I'm not familiar with the TT or the Falcon. In the ST an YM access will be five cycles minimum. If there is no rounding up (say, running from ROM or fast RAM) and no DMA taking bus ownership, then yes, it would be exactly 5 cycles. And if you somehow can avoid all processor overhead, then you could indeed write to the PSG every 5 cycles.
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