ijor wrote:Yes, the IR registers (as named in the Alien model) can be described as a kind of SHIFT array or FIFO. The FIFO/SHIFT is clocked by a LOAD pulse coming from MMU. No matter what, a LOAD pulse would push one word and discard the last one on the FIFO (the last word in the FIFO is the one that entered first).
Thx, it makes sense. If the new word was blocked instead, we would have very different effects.
It is not a real life example. I just simulated that DE is misaligned so that two words remained from the previous scan.
There are many situations that can lead to the pixel counter not stopping. The logic stops the counter when a Reload happens after DE was deasserted. That would normally be after the last LOAD coming from MMU. The pixel counter can't be stopped before the actual Reload because the Reload logic depends on it.
But if DE is misaligned as in the example you mention, a Reload won't happen at the end of the line after DE is deasserted. That's actually why two words remain in the IR buffers. Without the last Reload the pixel counter won't stop.
I was afraid the 2 words shift wasn't caused by the 'right off' trick.
I have two other questions if you please:
1. Are IR and RR always the same registers with a copy IR->RR every 16 cycles, or are those register functions swapped at reload (like a toggle, sending new words to the other registers while the current one is being shifted - don't know if I'm being clear ) ? If the former, does copying IR to RR take time?
2. Do the RR always rotate, or only when the pixel counter is enabled?