larsbrinkhoff wrote:The textbook answer is that there is an 18-cycle delay from the assertion of LOAD, until the first pixel is displayed ... I'm curious about the 2-cycle delay that is added on top of the loads. Has anyone has seen evidence for anything other than 2 cycles?
troed wrote:edit: It's possible (proposed by .. hmm .. Dio, maybe, it should be in the same thread) that the Shifter is running its 32MHz clock on the shifting registers completely desynchronized to external signals
ijor wrote:The other issue is clock shifting. The ST has a chain of clocks divisions, 32 MHz into 16 MHz, into 8 MHz, and even then into 2 MHz (plus some more). Each division produces a small delay. So each divided clock is not precisely aligned with the one being divided.
exxos wrote:It might be worth double checking on that. When I was testing the divisions, I got some odd results. Like 3ns between 32mhz and 16mhz on shifter, and 0ns between 16mhz and 8mhz on MMU IIRC.
I was talking to Rodolphe about this last year as those delays are pretty impossible even with todays tech. Its not impossible though. If Atari had some buffer chain which matched the cycle time exactly (minus the actual propagation delays of the signal),then each division would/could be half a cycle behind with a "slow" inverter and appear exactly in phase with 0ns delay (or near to).
Been looking on my USB stick for images.. this could be 8mhz 4mhz..
larsbrinkhoff wrote:I'm not a hardware person. This is my mental model, and how I percieve the terminology.
troed wrote:1) "Spectrum 512 black pixels" - one shift (cycle) happens before xxxxx-palette-lookup-available-something
larsbrinkhoff wrote:troed wrote:1) "Spectrum 512 black pixels" - one shift (cycle) happens before xxxxx-palette-lookup-available-something
Is there a (stable) test case for this?
ijor wrote:exxos wrote:If Atari had some buffer chain which matched the cycle time exactly ...
The chips don't have any buffer delay chain, and even if they had, it wouldn't be precise. That would require a PLL. But regardless of the theoretical possibility, nothing like that is implemented inside these chips.
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