ijor wrote:I will appreciate if somebody takes the time to answer the questions:
- What's exactly the behavior? It's every other 16 pixels are displayed at background color?
In low res, yes. In high res it's every fifth word. I haven't seen it in medium, but I haven't tried to provoke it either.
- It has some relation to the GLUE-MMU wakestates? It happens in all of them?
It can happen in all of them, but it's possible the wakestate has some influence sometimes.
- I thought the issue happens only when implementing Spectrum 512 effects. But I see it's not the case. That is another different Shifter wakeup issue?
Yes. I believe Spectrum 512 pixels to be a mismatch between external signals to the Shifter (Load, CS) and it's internal pixel/shift-clock. Or rather, Dio proposed that a few years ago and I agree
- It happens only when opening the borders?
Some sort of manipulation needs to take place, but it doesn't need to be border opening. It's enough to try to do the non-fullscreen 4-pixel sync scroll (Paulo's) and it will happen sometimes.
- Does it really have wakeup behavior? Which means that is not affected by hardware reset. Only by power cycling.
In some of the cases it seems to be reset-persistent, but it's also something affected by warming. If you watch my STNICCC 2015 presentation I show some examples at the end where it seems to be affected by the memory address (!) read as well.
ijor wrote:I don't understand why a FIFO model would explain the effect. If the problem is indeed that sometimes RR is not reloaded with IR, then it is probably a failure in, precisely, the RR reload logic. That should be the same regardless of IR being a FIFO or not. Or I am missing something?
In low res, where it's "every 16", there could be many simpler explanations, yes. However, for the same explanation to work in high res the behavior must be different. Of course, I'm basing this on Alien's explanation on how IR and RR work - other setups could also explain it.
If IR (four words) get filled, and then transferred to RR (four words) in low res, RR is then shifted out one pixel at a time (all registers together) and when they're empty IR should've been filled with four new words. If the copy from IR to RR fails, the next 16 pixels will be all zeros and IR fills up with four new words.
In high resolution, four words are read into IR, and one word at a time is shifted out from RR. When all RR words are empty a copy from IR is attempted, and if it fails only one word is shifted out as all zeros until the next attempt is made. Now, if IR wasn't a FIFO the next copy could not be made with graphics at the correct location for the next four words.
I hope the above makes sense. On the top of my head it would probably be possible to explain it with IR only being used as four words in low res, two in medium and one word in high (and then the same for RR). However, I don't know if that would then match up with all other known Shifter behavior (basically, how "stabilizers" manage to clear the registers).
Btw, do we know what happens exactly when both bits of the REZ registers are set?
I am pretty sure GLUE doesn't care, it mostly ignores REZ bit 0. But I'm unsure what SHIFTER does. What happens with the mono display?
This I don't know at all.