MegaSTE: Details of implementation of clock switching and cache?

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czietz
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MegaSTE: Details of implementation of clock switching and cache?

Postby czietz » Tue Jun 26, 2018 9:04 pm

Hello,

is there any document detailing how the 8/16 MHz clock switching and the cache are done in the MegaSTE? Of course, I know about the register at $FF8E21, but how is it implemented at hardware level with all these PALs? For example: As far as I know, access to the IO space is with the original 8 MHz timing. Is the clock dynamically switched between 8 MHz and 16 MHz? Or does the CPU one of the PALs insert waitstates when the CPU runs at 16 MHz?

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Greenious
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Re: MegaSTE: Details of implementation of clock switching and cache?

Postby Greenious » Tue Jun 26, 2018 11:04 pm

Afaik there is no such documentation.

However, every build I have seen of these maintain two state machines in logic, one simulating a 8MHz CPU towards the bus, and one simulating a xxMHz bus towards the CPU. So yes, waitstates are inserted as needed. (at 16MHz it's pretty easy to do, it get's more complicated at higher speeds.)

If you want to look closer at an accelerator implementing this I suggest the Mach16 buid from http://atari4ever.free.fr/
Updated my guides as of june 28th, 2016. Check'em out and feedback!
viewtopic.php?t=5040

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Re: MegaSTE: Details of implementation of clock switching and cache?

Postby ijor » Fri Jun 29, 2018 6:35 pm

I might be wrong, and I don't know much about the MSTe ... But I seem to remember something about the PALs switching the clock on the fly when accessing the external system. Might be it was about a third party accelerator and not about the MSTE?

czietz
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Re: MegaSTE: Details of implementation of clock switching and cache?

Postby czietz » Fri Jun 29, 2018 6:53 pm

In the meantime, I measured the clock in my MegaSTE. It does not switch on the fly depending on the address that is being accessed. Instead DTACK is delayed appropriately. However, ijor, you are right, some accelerators do switch the clock; that's my I asked.

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Re: MegaSTE: Details of implementation of clock switching and cache?

Postby SteveBagley » Fri Jun 29, 2018 10:46 pm

The PAL equations for some of the MegaSTE PALs are on the AtariHQ cdrom -- see Documents/Atari/TECHDOCS/MSTE/PALS

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