Check (2) by observing pin 22 of the CPU (BERR) as the unit is powered on. It should be high always. If there are logic low pulses, some component is malfunctioning and Glue is generating the error. Verify the clocks to Glue and Memory Controller and replace these components to verify them.
Sassa wrote:I noticed that the 6 TOS roms were different from each other : not only the markings but also the "looks" of the chips. "the guy" replaced it with random TOS chips from his bin.
One of them is th C101633-001 (1.02 HI french of the 2chips-set) ; I put it in the right HI socket then tried to make the LO part using a 32pin flash chip (SST29EE010). I did it using the french TOS rom I found online, romsplit in an emulator, and flashrom on linux with a realtec NIC.
Following the ST and Mega ST service manuals, I found that the CPU is held in HALT mode, with VCC on most pins of the ROMs.
I checked the reset inverters chip (unsoldered and socketed it) and it is good.
Using a saleae logic, I confirmed that BERR goes low 0.3s after startup : see the attached file.
Sassa wrote:When looking at the end of the capture, I can see that some addresses are accessed after the BERR signal. What dou you think about that ?
Users browsing this forum: Bing [Bot] and 2 guests