alanh wrote:I'm not sure what you are saying, but grab a picture of a 68000 bus cycle, and then show on that what you've done to the bus cycle with your accelerator.
I'm just saying /AS will arrive slightly early. If you "time" monster and assume /AS arrives on a 8MHz clock HI (which IIRC is stock timing) then the booster will set /AS low on the 8MHz low cycle.
This is a issue if you are running FF's for timings. As the first FF on stock timing (assuming a FF is in sync with the rising edge of the 8MHz clock) Then there will basically be 125ns (62ns on the 8MHz clock HI and 62ns on the 8MHz clock low) before the FF's propagates.
If however /AS arrives on a 8MHz clock low, it will likely fall mid-point in a 8MHz low, so it will then have about 30ns before the FF propagates. So the timings though a FF will have gone from 125ns to 30ns, which is when things screw up.
Though I don't know how your design works, its just a example of how things can go wrong if things are not synconised to the 8MHz clock.
Whatever you did with your original IDE interface, which was all TTL logic , that one works fine. Though its possible the delays though all the logic were enough for the circuit to still function as expected. Though its just a guess.
I can edit the 68000 datasheet timings if it helps, but all you need to do is just think /AS arrives on a 8MHz clock low, not a clock HI. Of course I don't know if that is the problem, but its the only timing I can think of which varies.
Of course 16/32Mhz will be in play on ROM access and when /AS is HI. Though unless you do any logic operations (like reset flip flops or counters or something) when /AS goes high, then that end of the cycle shouldn't be a problem.
This is just a example of what I am suggesting..
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