1040STe+ (STe w/ 286 CPU) PCB layout

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Re: 1040STe+ (STe w/ 286 CPU) PCB layout

Postby czietz » Thu Feb 16, 2017 5:59 pm

leech wrote:This is an awesome find. Would the graphics have been updated to handle EGA/VGA? Or just pass through at standard ST resolutions, which of course have a different pallette to EGA. Would have been odd to run dos games in that case.


From what I've seen, apart from the 286 and the IDE interface, this would have been a regular STe without any additional video hardware. Also, I think DOS games weren't the primary target, but rather productivity / business software -- much like with the AT Speed add on cards.

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Re: 1040STe+ (STe w/ 286 CPU) PCB layout

Postby exxos » Thu Feb 16, 2017 6:09 pm

Alan's original IDE interface works fine with my V2 booster, Monster doesn't however. Though I have 2 STFM monster versions where the IDE failed to work even on a stock machine, so I was unable to do any testing there. I have the STE version I got secondhand to figure out the issue with the 32MHz booster & the STE, but not got around to it yet. I never got PP's IDE design to work either which doesn't use any delay timings and also seems common on Amiga's. I am not sure how a fast CPU would work with that, the timings are somewhat screwy to start with. The only IDE solution which has ever worked for me is Alan's original IDE interface.

If people are using the "flip flop" method and using the clock to clock the FF's, then 16MHz mode likely screws up that idea. They will get clocked at 16MHz, but really it shouldn't matter since when the CPU accesses the bus, it switches to 8MHz mode. So there shouldn't be any reason why any existing hardware can't work as before.

The only exception to stock timings is /AS will reach the motherboard slightly faster than normal. Though that shouldn't affect anything anyway. Though if /AS is used as a reference point to triggering some FF's then likely the "count" will get screwed up. I simulated just that with the FF design. The FF's idea assuming that /AS arrives on a CLK8 HI, but if it arrives on a CLK8 LO, then it all goes to hell. It is the one reason I abandoned the FF idea with my WIP IDE design.

The way to tell is just to run /AS to monster via a FF clocked at 8Mhz to sync to the CLK8 high, That's the only thing I can think of. I just haven't got time to work on that at the moment. Maybe someone who wants to look into it can try it out for themselves..
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Re: 1040STe+ (STe w/ 286 CPU) PCB layout

Postby Maeke » Thu Feb 16, 2017 8:38 pm

joska wrote:
Maeke wrote:btw sure would be great if the schematics and the gals/pals files were recovered, this would allow us to reproduce the ide system atari was planning to use on the st line, the existing designs have a flow since they don't work if the cpu is boosted (from what i saw on ebay, the ide card for the mega-ste doesn't work at 16 Mhz, and we had proofs that the ppera design doesn't work with exxos's 32Mhz booster).


20 years ago I had a Mega ST with a C't IDE interface, which ppera's design is heavily influenced from. Actually, they're virtually the same except for the buffer on the C't. This interface worked just fine with my ADSpeed16. Also, the Falcon IDE works fine at 16/18/20/24/25MHz.

I have one of exxos' 16MHz boosters, and it doesn't work with the MonSTer. Don't know what's not working, it's not booting at all. I have another 16MHz accelerator that's working fine with it, but I don't know what the difference is. Tha PAK/20 is also running at 16MHz and is working with the MonSTer (and most likely other IDE-interfaces too).

I really don't see why the IDE interface shouldn't work with a 32MHz accelerator. The bus is accessed at 8MHz anyway. Actually, it should - in theory - be possible to access the IDE bus at 32MHz, if the logic is fast enough. I'd expect around 6-7Mb/s in that case, if you have fast-RAM to shuffle the data to.


Well i don't know either but i know it has been tried, and didn't work.

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Re: 1040STe+ (STe w/ 286 CPU) PCB layout

Postby joska » Thu Feb 16, 2017 8:52 pm

Maeke wrote:Well i don't know either but i know it has been tried, and didn't work.


That's because the booster does not access the bus exactly like the original 8MHz 68000. With some debugging of the booster I'm sure it will work.
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Re: 1040STe+ (STe w/ 286 CPU) PCB layout

Postby exxos » Thu Feb 16, 2017 9:03 pm

joska wrote:
Maeke wrote:Well i don't know either but i know it has been tried, and didn't work.


That's because the booster does not access the bus exactly like the original 8MHz 68000. With some debugging of the booster I'm sure it will work.


When it accesses the bus is runs in 8MHz so it's exactly like a stock CPU running without the booster, that was the whole point of the design. The only time it runs in 16MHz or (32MHZ on the STE) is when the CPU isn't accessing the bus, so the CPU's internal instructions run double speed. The only exception to that is the ROM where the CPU also runs at 16/32MHz. Though someone bypassed the ROM decoding, so it wasn't that anyway.

The only time the CPU runs faster than normal is like I said in my previous post which is where /AS reaches the bus slightly early, or /AS will go high slightly earlier than a stock machine. Though only Alan can answer how he has monster running. Without more information it would just be near endless guessing.

Another test, just cut the 8MHz pin to monster and just feed it direct to the 8MHz clock from the MMU or wherever. Then monster will always get the stock clock as normal.
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Re: 1040STe+ (STe w/ 286 CPU) PCB layout

Postby SteveBagley » Thu Feb 16, 2017 11:07 pm

czietz wrote:From what I've seen, apart from the 286 and the IDE interface, this would have been a regular STe without any additional video hardware. Also, I think DOS games weren't the primary target, but rather productivity / business software -- much like with the AT Speed add on cards.


Not just like the AT-speed, there's stuff on that CD that makes me think it probably is an AT-speed built into the motherboard… (Arcdoc1.pdf lists the AT-Speed Read.me as being documentation for the STE+, for instance)

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Re: 1040STe+ (STe w/ 286 CPU) PCB layout

Postby Maeke » Fri Feb 17, 2017 12:52 am

I recall having read this was actually this, found it: viewtopic.php?t=23282#p209260

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Re: 1040STe+ (STe w/ 286 CPU) PCB layout

Postby czietz » Fri Feb 17, 2017 6:42 am

SteveBagley wrote:Not just like the AT-speed, there's stuff on that CD that makes me think it probably is an AT-speed built into the motherboard… (Arcdoc1.pdf lists the AT-Speed Read.me as being documentation for the STE+, for instance)


Using a photo of the AT Speed (http://wiki.newtosworld.de/index.php?ti ... n_Sack.jpg) I exemplarily followed some traces in the 1040STe+ layout that I found -- and they indeed seem to match. However, as there is no way of knowing what's inside the PALs/GALs, one cannot know for sure if they are identical. Also, there is little technical documentation about the 1040STe+ and none (that I know of) about the inner workings of an AT Speed to compare.

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Re: 1040STe+ (STe w/ 286 CPU) PCB layout

Postby alanh » Fri Feb 17, 2017 8:36 am

exxos wrote:The only time the CPU runs faster than normal is like I said in my previous post which is where /AS reaches the bus slightly early, or /AS will go high slightly earlier than a stock machine. Though only Alan can answer how he has monster running. Without more information it would just be near endless guessing.


Unfortunately, that's not stock then. Any modification to the bus signals can cause failure over a stock machine. AS is relied upon to be exact.
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Re: 1040STe+ (STe w/ 286 CPU) PCB layout

Postby SteveBagley » Fri Feb 17, 2017 8:43 am

czietz wrote:Using a photo of the AT Speed (http://wiki.newtosworld.de/index.php?ti ... n_Sack.jpg) I exemplarily followed some traces in the 1040STe+ layout that I found -- and they indeed seem to match. However, as there is no way of knowing what's inside the PALs/GALs, one cannot know for sure if they are identical. Also, there is little technical documentation about the 1040STe+ and none (that I know of) about the inner workings of an AT Speed to compare.


The hardware methodology of the STE+ is documented in the service manual (on the CD) -- a write to a specific memory location causes the a bus request to freeze the 68K, while releasing control of the 80286 to run and an IO request from the 80286 releases the bus and reawakens the 80286…

I guess one way to check is to look at the AT-speed software and see if it used similar addresses (other than trying to read the GALs of the surviving STE+s…)

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Re: 1040STe+ (STe w/ 286 CPU) PCB layout

Postby joska » Fri Feb 17, 2017 10:20 am

exxos wrote:When it accesses the bus is runs in 8MHz so it's exactly like a stock CPU running without the booster, that was the whole point of the design.


If it was *exactly* the same, then it would work, wouldn't it? So it's most likely different enough to cause problems for other add-ons.
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Re: 1040STe+ (STe w/ 286 CPU) PCB layout

Postby exxos » Fri Feb 17, 2017 10:42 am

joska wrote:
exxos wrote:When it accesses the bus is runs in 8MHz so it's exactly like a stock CPU running without the booster, that was the whole point of the design.


If it was *exactly* the same, then it would work, wouldn't it? So it's most likely different enough to cause problems for other add-ons.


Nope, see my previous comments.
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Re: 1040STe+ (STe w/ 286 CPU) PCB layout

Postby exxos » Fri Feb 17, 2017 10:49 am

alanh wrote:
exxos wrote:The only time the CPU runs faster than normal is like I said in my previous post which is where /AS reaches the bus slightly early, or /AS will go high slightly earlier than a stock machine. Though only Alan can answer how he has monster running. Without more information it would just be near endless guessing.


Unfortunately, that's not stock then. Any modification to the bus signals can cause failure over a stock machine. AS is relied upon to be exact.


On that bases if you added a tweak to your code to wait for /AS to be high on a CLK8 cycle before it starts the transfer then it would be a really easy fix.
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Re: 1040STe+ (STe w/ 286 CPU) PCB layout

Postby alanh » Fri Feb 17, 2017 11:00 am

exxos wrote:
alanh wrote:
exxos wrote:The only time the CPU runs faster than normal is like I said in my previous post which is where /AS reaches the bus slightly early, or /AS will go high slightly earlier than a stock machine. Though only Alan can answer how he has monster running. Without more information it would just be near endless guessing.


Unfortunately, that's not stock then. Any modification to the bus signals can cause failure over a stock machine. AS is relied upon to be exact.


On that bases if you added a tweak to your code to wait for /AS to be high on a CLK8 cycle before it starts the transfer then it would be a really easy fix.


I'm not sure what you are saying, but grab a picture of a 68000 bus cycle, and then show on that what you've done to the bus cycle with your accelerator.
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Re: 1040STe+ (STe w/ 286 CPU) PCB layout

Postby exxos » Fri Feb 17, 2017 11:34 am

alanh wrote:I'm not sure what you are saying, but grab a picture of a 68000 bus cycle, and then show on that what you've done to the bus cycle with your accelerator.


I'm just saying /AS will arrive slightly early. If you "time" monster and assume /AS arrives on a 8MHz clock HI (which IIRC is stock timing) then the booster will set /AS low on the 8MHz low cycle.

This is a issue if you are running FF's for timings. As the first FF on stock timing (assuming a FF is in sync with the rising edge of the 8MHz clock) Then there will basically be 125ns (62ns on the 8MHz clock HI and 62ns on the 8MHz clock low) before the FF's propagates.

If however /AS arrives on a 8MHz clock low, it will likely fall mid-point in a 8MHz low, so it will then have about 30ns before the FF propagates. So the timings though a FF will have gone from 125ns to 30ns, which is when things screw up.

Though I don't know how your design works, its just a example of how things can go wrong if things are not synconised to the 8MHz clock.

Whatever you did with your original IDE interface, which was all TTL logic , that one works fine. Though its possible the delays though all the logic were enough for the circuit to still function as expected. Though its just a guess.

I can edit the 68000 datasheet timings if it helps, but all you need to do is just think /AS arrives on a 8MHz clock low, not a clock HI. Of course I don't know if that is the problem, but its the only timing I can think of which varies.

Of course 16/32Mhz will be in play on ROM access and when /AS is HI. Though unless you do any logic operations (like reset flip flops or counters or something) when /AS goes high, then that end of the cycle shouldn't be a problem.

This is just a example of what I am suggesting..

read_cycle.png
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Re: 1040STe+ (STe w/ 286 CPU) PCB layout

Postby alanh » Fri Feb 17, 2017 12:42 pm

So AS is going low in S1, that just looks wrong.
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Re: 1040STe+ (STe w/ 286 CPU) PCB layout

Postby joska » Fri Feb 17, 2017 5:04 pm

exxos wrote:
joska wrote:If it was *exactly* the same, then it would work, wouldn't it? So it's most likely different enough to cause problems for other add-ons.


Nope, see my previous comments.


I see that you describe precisely how the booster deviates from the stock 8MHz 68000.
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Re: 1040STe+ (STe w/ 286 CPU) PCB layout

Postby czietz » Fri Feb 17, 2017 6:56 pm

SteveBagley wrote:The hardware methodology of the STE+ is documented in the service manual (on the CD) -- a write to a specific memory location causes the a bus request to freeze the 68K, while releasing control of the 80286 to run and an IO request from the 80286 releases the bus and reawakens the 80286…


Unfortunately, the sentence you paraphrase above is more or less the only thing that is documented on the 68K <-> x86 interface of the STe+: reading 0xFFFC80 will stop the 68000 and start the 80286, any I/O instruction on the 80286 will switch control back to the 68000. As the service manual is incomplete/in a very early stage, nothing is written about how data is exchanged between the CPUs, how the memory map as seen from the 80286 is etc.

The AT-Speed software indeed does read from 0xFFFC80 (among other addresses). Whether this is a coincidence or not, I do not know.

PS: Wouldn't it be appropriate to discuss booster and IDE compatibility in a separate thread?

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Re: 1040STe+ (STe w/ 286 CPU) PCB layout

Postby exxos » Fri Feb 17, 2017 7:02 pm

czietz wrote:
PS: Wouldn't it be appropriate to discuss booster and IDE compatibility in a separate thread?


Yes, I'm done with the thread anyway, posts can be moved or deleted out as far as I am concerned.
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