1040STe+ (STe w/ 286 CPU) PCB layout

[czietz]

Hello,

you might have heard of the 1040STe+, a planned but never released STe with an additional 286 CPU so that it could run MS-DOS as well. Prototypes are said to exist.

Now, attached is another recent find of mine: the PCB layout of said machine, dated 1991. I'm still looking into this, but some things can be seen at first glance: The basis of the STe+ is the newer STe layout with the COMBO chip. By moving the Blitter into the COMBO chip, Atari had space on the PCB for the 286 CPU and the glue logic to interface it to the rest of the machine. See the lower right hand corner. Also the STe+ would have had an IDE drive (big empty space on the left), for which the seldom used joystick/paddle/lightpen ports of the STe were removed.

1040steplus.png

[exxos]

Awesome!

[troed]

Wow! Never heard of.

[Maeke]

i've seen a bad photocopy of this layout, but it was hard to see the details.

Well it wasn't a full layout, the track weren't on it: http://atariage.com/forums/topic/209914 ... 0f-issue/#
btw it seems some developpers received a fully assembled 1040 ste+ from atari mexico.

[soviet9922]

This mean that technically this board can be fabricated now ?

[Maeke]

This mean that technically this board can be fabricated now ?

Well even if it can, if you don't have a square dma at hands, it will be for naught.
btw we have the layout, but not the schematics afaik, neither have we the gals or pals dumps.
Maybe it's in the files besides the layout, but it's under investigations right now, hoping it's not corrupted.

[mikro]

Wow, where did you find it?

[Maeke]

Wow, where did you find it?

viewtopic.php?f=15&t=30280&p=300210#p300210

http://www.chzsoft.de/asic-web/

[mikro]

Thanks, I thought all the PCBs are already explored, great find then. :)

[czietz]

Thanks, I thought all the PCBs are already explored, great find then.

There are a lot of files in ancient file formats. It seems no one managed to (or bothered to?) explore them. For example several PCB layouts in CADSTAR for DOS (pre-version 7) file format. In the end I asked a PCB design specialist to convert these for a fee, so that I could show you the results.

[mikro]

Big thumb up for that, mate!

[Maeke]

btw sure would be great if the schematics and the gals/pals files were recovered, this would allow us to reproduce the ide system atari was planning to use on the st line, the existing designs have a flow since they don't work if the cpu is boosted (from what i saw on ebay, the ide card for the mega-ste doesn't work at 16 Mhz, and we had proofs that the ppera design doesn't work with exxos's 32Mhz booster).

[TXG/MNX]

I got a falcon030 with a falcon speed that has a 286 so basicly they add such expansion to the PCB

[exxos]

btw sure would be great if the schematics and the gals/pals files were recovered, this would allow us to reproduce the ide system atari was planning to use on the st line, the existing designs have a flow since they don't work if the cpu is boosted (from what i saw on ebay, the ide card for the mega-ste doesn't work at 16 Mhz, and we had proofs that the ppera design doesn't work with exxos's 32Mhz booster).

Problem with most of the IDE designs they use the 8Mhz clock for timings. The IDE bus cycle while its total cycle length matches the IDE timing cycle, you can't use the 8Mhz clock reliably to time stuff. This is why I gave up with trying to use the 8Mhz clock. Technically the IDE interface should still work with 32MHz as the booster switches to 8MHz during a ST bus cycle, but it doesn't. I did buy a second hand monster for the STE to diagnose the issue, but again, I just don't have time to try things out.

I guess if the IDE interfaces work reliable at 8MHz then if the clock pin is cut and feed back with the 8Mhz clock then it may work. Or the only other possible thing could be that the booster sets /AS slightly faster than expected, so Monster might not like that. running /
AS though a clocked FF's to re-sync /AS might cure it. Though I have no idea how Alan is timing monster. Even so, I just gave up with that method. I never got ppera's design to work either.

In anycase, the IDE design I have done (likely won't get tested for a long time yet as just to busy with other things) uses timers to match the published IDE timing specification. The timings match IDE specs exactly, also it doesn't use the system clock (8MHz or 32MHz at all) so the design would be future proof for all boosters.

[czietz]

btw sure would be great if the schematics and the gals/pals files were recovered, this would allow us to reproduce the ide system atari was planning to use on the st line, the existing designs have a flow since they don't work if the cpu is boosted

As the 1040STe+ would have run with 8 MHz only, I don't think Atari designed the IDE interface for different clock speeds, though. Possibly it's just the IDE interface of the ST Book condensed in a single GAL/PAL.

[Maeke]

btw sure would be great if the schematics and the gals/pals files were recovered, this would allow us to reproduce the ide system atari was planning to use on the st line, the existing designs have a flow since they don't work if the cpu is boosted

As the 1040STe+ would have run with 8 MHz only, I don't think Atari designed the IDE interface for different clock speeds, though. Possibly it's just the IDE interface of the ST Book condensed in a single GAL/PAL.

Well since i don't have a st book and never had one, i don't know about it's ide interface.

[Maeke]

btw sure would be great if the schematics and the gals/pals files were recovered, this would allow us to reproduce the ide system atari was planning to use on the st line, the existing designs have a flow since they don't work if the cpu is boosted (from what i saw on ebay, the ide card for the mega-ste doesn't work at 16 Mhz, and we had proofs that the ppera design doesn't work with exxos's 32Mhz booster).

Problem with most of the IDE designs they use the 8Mhz clock for timings. The IDE bus cycle while its total cycle length matches the IDE timing cycle, you can't use the 8Mhz clock reliably to time stuff. This is why I gave up with trying to use the 8Mhz clock. Technically the IDE interface should still work with 32MHz as the booster switches to 8MHz during a ST bus cycle, but it doesn't. I did buy a second hand monster for the STE to diagnose the issue, but again, I just don't have time to try things out.

I guess if the IDE interfaces work reliable at 8MHz then if the clock pin is cut and feed back with the 8Mhz clock then it may work. Or the only other possible thing could be that the booster sets /AS slightly faster than expected, so Monster might not like that. running /
AS though a clocked FF's to re-sync /AS might cure it. Though I have no idea how Alan is timing monster. Even so, I just gave up with that method. I never got ppera's design to work either.

In anycase, the IDE design I have done (likely won't get tested for a long time yet as just to busy with other things) uses timers to match the published IDE timing specification. The timings match IDE specs exactly, also it doesn't use the system clock (8MHz or 32MHz at all) so the design would be future proof for all boosters.

If you need someone to test your design (i'm Thibaut Guillet from atari st and ste users on facebook).

[1st1]

Well since i don't have a st book and never had one, i don't know about it's ide interface.

You can study it in ST-Book circuit diagram. http://dev-docs.atariforge.org/files/ST ... 8-1992.pdf

[Maeke]

Well since i don't have a st book and never had one, i don't know about it's ide interface.

You can study it in ST-Book circuit diagram. http://dev-docs.atariforge.org/files/ST ... 8-1992.pdf

Thanks, will take me some times to decipher though, i'm more accustomed to the french symbols and schematics.

[leech]

This is an awesome find. Would the graphics have been updated to handle EGA/VGA? Or just pass through at standard ST resolutions, which of course have a different pallette to EGA. Would have been odd to run dos games in that case.

[alanh]

btw sure would be great if the schematics and the gals/pals files were recovered, this would allow us to reproduce the ide system atari was planning to use on the st line, the existing designs have a flow since they don't work if the cpu is boosted (from what i saw on ebay, the ide card for the mega-ste doesn't work at 16 Mhz, and we had proofs that the ppera design doesn't work with exxos's 32Mhz booster).

The MonSTer with it's IDE works fine at 8MHz and 16MHz on the MegaSTE.

[Mindthreat]

That's really cool =D Any chance the PCB layout for the Falcon board exists as well?

[alanh]

Falcon has IDE already, and it works fine.

[Maeke]

btw sure would be great if the schematics and the gals/pals files were recovered, this would allow us to reproduce the ide system atari was planning to use on the st line, the existing designs have a flow since they don't work if the cpu is boosted (from what i saw on ebay, the ide card for the mega-ste doesn't work at 16 Mhz, and we had proofs that the ppera design doesn't work with exxos's 32Mhz booster).

The MonSTer with it's IDE works fine at 8MHz and 16MHz on the MegaSTE.

Didn't talk about the monsterste. btw i'm not bothered by the MegaSTE since i don't have one, but by the STE @ 32Mhz.

[joska]

btw sure would be great if the schematics and the gals/pals files were recovered, this would allow us to reproduce the ide system atari was planning to use on the st line, the existing designs have a flow since they don't work if the cpu is boosted (from what i saw on ebay, the ide card for the mega-ste doesn't work at 16 Mhz, and we had proofs that the ppera design doesn't work with exxos's 32Mhz booster).

20 years ago I had a Mega ST with a C't IDE interface, which ppera's design is heavily influenced from. Actually, they're virtually the same except for the buffer on the C't. This interface worked just fine with my ADSpeed16. Also, the Falcon IDE works fine at 16/18/20/24/25MHz.

I have one of exxos' 16MHz boosters, and it doesn't work with the MonSTer. Don't know what's not working, it's not booting at all. I have another 16MHz accelerator that's working fine with it, but I don't know what the difference is. Tha PAK/20 is also running at 16MHz and is working with the MonSTer (and most likely other IDE-interfaces too).

I really don't see why the IDE interface shouldn't work with a 32MHz accelerator. The bus is accessed at 8MHz anyway. Actually, it should - in theory - be possible to access the IDE bus at 32MHz, if the logic is fast enough. I'd expect around 6-7Mb/s in that case, if you have fast-RAM to shuffle the data to.