IDE is very simple and - as Greenios stated - well documented on several websites. I spent a long evening to get my own IDE-interface (and flash-ROM) set up and working on breadboard based on the information on ppera's website. And then another week making a permanent implementation on veroboard...
Flashable ROM in it's simplest form is also extremely simple, all you have to do is to create a DTACK for writes to the ROM address range. In my STM I have IDE and flashable ROM (both fc0000 and e00000) implemented in a single GAL.
Yeah I have to generate DTACK for the fast-rom anyway. Its just DTACK with WRITE on that address range. I followed Putniks design for IDE as it seems to be proven, but as mentioned just in another post, I've tweaked it a fair bit so its not tested.
joska wrote:This has been done years ago. The Suska development started this way.
Yeah, though that has come up a few times before, I even posted Wolgangs reply. Even though the chipsets appear to be all single, He says he never did that. He said you can't just replace one chip and it will work like it may look on the images on his site. So while the bulk of the work may be done, there is still no "drop in replacement". I no nothing about VHDL and likely will not look into that as I just don't have time.
Like I mentioned before though, if someone can develop a "Drop in" FPGA clone, I can design the hardware to use the IC, but thats as far as I am willing to do with it. Someone else will have to do the code. As mentioned before, tweaks can be done to improve the design likely easily. Though getting a FPGA to literally replace a chip like GLUE is going to be a lot of work.