Code: Select all
!UDS = !DS20 & !DS20_1 & !A0;
UDS.oe = HIGHZ;
!LDS = !DS20 & !DS20_1 & SIZ1
# !DS20 & !DS20_1 & !SIZ0
# !DS20 & !DS20_1 & A0;
LDS.oe = HIGHZ;
rpineau wrote:I might also try to find a STE and put a TOS 2.06 on it for testing as the MegaSTE might behave differently in term of signal quality
rpineau wrote:Ok, I just checked the 68020 UM, and /DS is also delayed on write so UDS and LDS will be properly delayed and match the 68000 write cycle. But thank for correcting me.
Now I still need to find where the /BG issue comes from.
rpineau wrote:If more people want to help I have enough part to build a 3rd board. I would provide the board for free but you need to get the JTAG programmer for the CPLD we're using (ATF1504 in the dev version, it's the same programmer for the whole ATF1500 family).
frank.lukas wrote:... very beautiful ))
I'm waiting for a version for the normal Atari ST.
MasterOfGizmo wrote:I found this image in another forum. Seems to be exactly what you guys are doing here.
http://www.webmaster-imho.de/wp-content ... m68020.png
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