mpattonm wrote:Switching DSP to 56301 will be a little setback, but hey - its a fun project and thats where the fun is. So back to the schematics.
Awesome. Just want to mention it - in this case some minor changes to the TOS are going to be needed.
Overclocking the system bus will however not overclock I/O subsystem so that should remain stable.
Are you sure that NG schematics reflect that idea? I mean you're still sourcing the SDMA with CPUCLKA so whatever happens in the Combel will get mirrored on the output. In this particular case, ACIAs wont work anymore (CLK8).
I'm not sure how all the issues related to clock patching will matter there now (I hope they wont at all), so in an ideal case I would do:
- have separate CLK8 for ACIAs coming from your PLL
- have CPUCLKA-C as in your schematics but with that exception that I would allow yet another source for the CPU/FPU - for the cases where one would replace CPU/FPU with their PGA variants (33-50 MHz, possible overclocking >50 MHz!)
In case the troubles with clock signals remain even in your new design, then I would definitely cut CPUCLKA + CPUCLKB from the Combel and had them sourced separately as the CenturboII does.
If there is enough room, I will also implement DIP-16 socket for original 32,084988MHz crystal generator. With that in place, user will have an option to switch from generic PLL to original Falcon clock frequencies for RGB monitor support and cycle-perfect Falcon demo compatibility.
Actually all you need is to drive this signal to Videl's VID32 pin (other turbo cards usually did this on the external pin but that resulted in 50% compatibility - yes, you could patch system calls but all demos using Videl's 32 MHz directly refuse to work without a patch).EDIT:
OK, I got confused. ACIA takes 500 kHz and yes, your schematics do reflect that. :-P