Verilog for noobs

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sebdel
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Verilog for noobs

Postby sebdel » Tue Jan 19, 2016 12:30 pm

Hi,
First of all, this is a complete stab in the dark. I know this forum is a low traffic forum, but I just can't find a place on the internet with a thriving community of Verilog hackers :lol:
So: Would there be people on this forum that are willing to answer basic Verilog questions for beginners ?
I am just starting to play with the Quartus tools on the Mist and have been making just enough progress to be more and more frustrated with my inability to understand the most basic stuff in Verilog. As soon as I think I understood something, I'm proven wrong on my next modification.
If anyone is interested, I'll just start dumping code snippets of my failures in there for review/explanations.

Thanks!
Seb

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Re: Verilog for noobs

Postby Newsdee » Tue Jan 19, 2016 3:11 pm

As a Verilog n00b myself, I feel I need more EE luggage to understand how to do things in Verilog. Many tutorials focus on the language but I'm more at a level that I need to understand the fundamental electronics we are supposed to drscribe with it...

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Re: Verilog for noobs

Postby alexh » Tue Jan 19, 2016 6:25 pm

(System) Verilog is my day job. What are you interested in knowing?

Put the code snippets with the design intent and I'll help you understand them.

If you can understand the concept of multi-threaded software. And you know the syntax for ANSI C then it is relatively easy to pick up.

The hardest concept in HDL to a new learner is usually combinatorial logic vs sequential logic. Next is delta delays. Third is CDC (clock domain crossing) which can catch out even the most seasoned HDL engineer. Then probably the infinite parallel capabilities.

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Re: Verilog for noobs

Postby alexh » Tue Jan 19, 2016 6:31 pm

As for other places to discus things... there was the MiniMig forum... but I dunno if anyone goes there anymore?

http://www.minimig.net/

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Re: Verilog for noobs

Postby mfro » Tue Jan 19, 2016 8:50 pm

If you did programming (e.g. C) before, the essential thing you need to learn fast is that you must forget most of what you have learned there before. There is one fundamental difference that's not so easy to grasp at first:

in C (or any "traditionally programming" you might have done before), all the things you code happen sequentally. Doing things in parallel requires much additional effort.

In an FPGA, it's just the other way round: everything happens in parallel, at the same time. If you want to have things happen sequentially, this requires extra effort over here.

Might sound easy, but isn't, at least not at the beginning.

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Re: Verilog for noobs

Postby sebdel » Wed Jan 20, 2016 1:07 pm

Awesome, here we go.
So, re: "everything happens in parallel" -> is this always true ? Here's a problem I ran into:
First, the working code, before modification (in full:https://github.com/mist-devel/mist-board/blob/master/tutorials/soc/lesson9/vga.v):

Code: Select all

reg [7:0] pixel;
reg dark_pix;

// read VRAM for video generation
always@(posedge pclk) begin

   if((v_cnt < V) && (h_cnt < H)) begin
      // increase video counter after each pixel
      if(h_cnt[1:0] == 2'd3)
         video_counter <= video_counter + 14'd1;

      pixel <= vmem[video_counter];               // read VRAM
      dark_pix <= 1'b0;
      
      // draw cursor
      if(((cursor_map_y+8'd8) > v_cnt[9:2]) &&
         ((cursor_map_y <= v_cnt[9:2]) || (cursor_map_y > 248)) &&
         ((cursor_map_x+8'd8) > h_cnt[9:2]) &&
         ((cursor_map_x <= h_cnt[9:2]) || (cursor_map_x > 248))  ) begin

         if(cursor_mask_pix)
            pixel <= cursor_data_pix?cursor_col_1:cursor_col_0;
         else if(cursor_data_pix)
            dark_pix <= 1'b1;
      end
      
   end else begin
           // video counter is manipulated at the end of a line outside
           // the visible area
      if(h_cnt == H+HFP) begin
         // the video counter is reset at the begin of the vsync
              // at the end of three of four lines it's decremented
              // one line to repeat the same pixels over four display
              //  lines
         if(v_cnt == V+VFP)
            video_counter <= 14'd0;
         else if((v_cnt < V) && (v_cnt[1:0] != 2'd3))
            video_counter <= video_counter - 14'd160;
      end
         
      pixel <= 8'h00;   // color outside visible area: black
      dark_pix <= 1'b0;
   end
end

So, this is from the mist tuto where a hw cursor is inserted in the video signal. If you look at the pixel register, it seems that it is initialized with the vmem[video_counter] and then overwritten with the cursor_data, on the same @(posedge pclk). So, it looks like 2 assignments one after the other right ?
So, I just did this. Right after the pixel <= vmem[video_counter] statement, I inserted :

Code: Select all

if (pixel == key_value)
    pixel <= key_color;

in an attempt to have one color on the screen that acts as a "background color".
And it failed. As soon as it met the first pixel equals to key_value, all other pixels on the screen were with key_color. As if, from now on, the if statement were always true. Note that I had chosen key_value == key_color so I can see how that could be true if this statement was evaluated "alone". But why is it not overwritten by the previous statement then ?

I made it worked eventually by introducing intermediate regs, but I still don't understand why it didn't work for me, and it works for the hw cursor. (same with dark_pix by the way, it is also assigned multiple times. How is that possible ?)

Thanks!
Seb

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Re: Verilog for noobs

Postby wongck » Wed Jan 20, 2016 1:37 pm

mfro wrote:If you did programming (e.g. C) before, the essential thing you need to learn fast is that you must forget most of what you have learned there before.


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Re: Verilog for noobs

Postby alexh » Wed Jan 20, 2016 1:40 pm

A very very quick glance.

If you look at the pixel register, it seems that it is initialized with the vmem[video_counter] and then overwritten with the cursor_data, on the same @(posedge pclk). So, it looks like 2 assignments one after the other right ?


No. You're thinking C-code where each line is executed sequentially.

Individual lines inside sequential processes don't get executed sequentially. They are a parallel operation. Think of it as assignments lower down a sequential always process (if reachable) as overriding previous ones. But the assignment doesn't actually take place until the next "posedge pclk" (i.e. the end of the always process).

So (unlike C-code) you cannot use a comparator operator after an assignment in a sequential process and expect the assignment to have taken place.

(Unless you use a blocking assignment also known as a variable in VHDL. However the use of blocking assignments in sequential processes is not good practice.)

What you actually wrote is comparing the PREVIOUS value of pixel with key_value.

I believe what you might have wanted was :

Code: Select all

if (vmem[video_counter] == key_value)
    pixel <= key_color;

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Re: Verilog for noobs

Postby sebdel » Wed Jan 20, 2016 4:58 pm

Great, that's exactly the kind of help I need :)
Ok, I understand better. So, statements are all evaluated in parallel and the order in which they are written decides of which prevails in case of conflict.
And everything that is assigned with "<=" is applied at next pass.
So this:

Code: Select all

     if(h_cnt[1:0] == 2'd3)
         video_counter <= video_counter + 14'd1;
      pixel <= vmem[video_counter];               // read VRAM

is equivalent to this:

Code: Select all

      pixel <= vmem[video_counter];               // read VRAM
      if(h_cnt[1:0] == 2'd3)
         video_counter <= video_counter + 14'd1;
?
I had another problem but I need to reproduce it. I *think* it had to do with using a "reg" in a "assign" statement. That didn't work until I added a "wire" in between (maybe ?). I'll post it here.

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Re: Verilog for noobs

Postby alexh » Wed Jan 20, 2016 6:27 pm

Yes. Those two are equivalent.

Reg type is used in both combinatorial and sequential always processes. Rather strangely it does not mean a register (flipflop).

Wire is used in structural verilog. Wiring and assigns.

I get the two wrong quite a lot especially if I've changed something from one to the other

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Re: Verilog for noobs

Postby mfro » Fri Jan 22, 2016 8:55 am

wongck wrote:
mfro wrote:If you did programming (e.g. C) before, the essential thing you need to learn fast is that you must forget most of what you have learned there before.


OMG that sound like Yoda..... https://www.youtube.com/watch?v=z4jeREy7Pbc


Yes. And you just feel like young Luke at the beginning: everything you know doesn't seem to apply anymore ... :D

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Re: Verilog for noobs

Postby alexh » Fri Jan 22, 2016 9:30 am

I've done HDL for 20 years and it's just logic programming language just like other logic programming languages. Just highly parallel. A good knowledge of C is invaluable for Verilog. Just as C++ is invaluable for SystemVerilog


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