simulation files for ddr3 memory

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SKuRGe911
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simulation files for ddr3 memory

Postby SKuRGe911 » Wed Oct 10, 2018 1:27 am

Does anyone have a ddr3 verilog or VHDL simulation file for the ram that is on the de10 nano or more specifficly the interface that the ddr3 has with the MiSTer system. Ive found some generic ones but they have many other pins on them which the MiSTer doesn't use.
Any help i would be grateful.

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Re: simulation files for ddr3 memory

Postby Sorgelig » Wed Oct 10, 2018 5:06 am

I don't know for what purpose you need it, but FPGA part access DDR3 memory through Avalon->MPFE interface, which has nothing common with DDR3 native memory interface. DDR3 is handled by hardware controller.
All you need is simulation of AnalonMM interface.

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Re: simulation files for ddr3 memory

Postby ijor » Wed Oct 10, 2018 6:43 pm

Just be careful and remember that the interface gives you access to the whole DDR ram space. MiSTer has Linux configured to use the lower half of the 1GB only, and the upper half is reserved for the FPGA side. But there is no protection enforced and there is no automatic offset adjustment. If you attempt to write to the lower half, the controller would happily comply and you'll overwrite Linux RAM space.

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Re: simulation files for ddr3 memory

Postby SKuRGe911 » Mon Oct 15, 2018 1:56 am

Its not that i'm lazy. I am pretty new to fpga development. I tried to generate a test bench for vip and it didn't work. Could you point me in the direction of how to get or create a simulation for the ddr3 ram. With out it I cant go any further with my exploration of the MiSTer.
Any help would be hugely appreciated.

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Re: simulation files for ddr3 memory

Postby ijor » Mon Oct 15, 2018 10:10 am

Simulating Vip and the HPS is not a simple task at all and I wouldn't recommend it to somebody new at FPGA development.

If you are not lazy, you might need to study the Cyclone V handbook. Check chapter 29: Simulating the HPS components. Note again that the FPGA side never accesses the DDR ram directly. It only accesses the MPFE interface.

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Re: simulation files for ddr3 memory

Postby Sorgelig » Mon Oct 15, 2018 12:59 pm

I think even MPFE is not required for simulation. VIP uses AvalonMM interface to access the memory.
I'm not familiar with simulation, but i believe AvalonMM should be an essential part of simulation components.

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Re: simulation files for ddr3 memory

Postby ijor » Mon Oct 15, 2018 1:48 pm

Sorgelig wrote:I think even MPFE is not required for simulation. VIP uses AvalonMM interface to access the memory.
I'm not familiar with simulation, but i believe AvalonMM should be an essential part of simulation components.


It depends on what he wants to simulate and for what purpose. It is really not clear at all what he wants to do.

You can't simulate just the Avalon MM interface by itself. The interface is just a set of signals. You have to simulate an Avalon MM slave if you want a simulation model to drive the interface. But yes, depending on the type of simulation you want, the slave doesn't have to be an MPFE model.

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Re: simulation files for ddr3 memory

Postby SKuRGe911 » Wed Oct 17, 2018 12:50 am

Thank you for your help. You wanted to know what i'm coding. I'm just experimenting with the zip cpu core trying to make a system as a computer that never would have existed. Its a 32 bit core so I would like the ddr3 ram to use in it. I was fooling around with the archi core's memory for sdram but was just wanting to test out the other ram. I'm going to read what you recommended. Thanks.


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