Snes on FPGA may get sof file release for de 10 nano mister

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Snes on FPGA may get sof file release for de 10 nano mister

Postby uigiflip » Sun Jun 03, 2018 5:20 am

Reply from my email:-

Thanks for your e-mail.

Currently, I seem to get MiSTer system from other supporters.
However, the source code can not be open source.
I plan to release a sof file of SNES on FPGA for MiSTer.

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Re: Snes on FPGA may get sof file release for de 10 nano mister

Postby Newsdee » Sun Jun 03, 2018 5:46 am

Nobody is forcing authors to open source cores, as long as it is entirely their own work.

Looking forward to it!

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Re: Snes on FPGA may get sof file release for de 10 nano mister

Postby Sorgelig » Sun Jun 03, 2018 6:00 am

MiSTer needs RBF file in order to load from Menu.

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Re: Snes on FPGA may get sof file release for de 10 nano mister

Postby uigiflip » Sun Jun 03, 2018 6:27 am

Can't it be compiled like the ti99 4a core
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Re: Snes on FPGA may get sof file release for de 10 nano mister

Postby NegSol » Sun Jun 03, 2018 9:34 am

uigiflip wrote:Can't it be compiled like the ti99 4a core


Sadly no - not without the source to compile it from. However, at least an SOF would enable use to flash the FPGA temporarily for testing out the core - but really that is all it is good for ... testing. :shrug:

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Re: Snes on FPGA may get sof file release for de 10 nano mister

Postby hlide » Sun Jun 03, 2018 9:53 am

If the author has a MiSTer and has the license for Quartus Prime Standard, he can:
- take a MiSTer core project, adapt it to put his source and make it work with MiSTer.
- build it to get an RBF file.
- publish the RBF file.
- document how to put external dependencies (ROM for instance).

Obviously, if some major changes may happen in the common stuff (menu, MiSTer interface), the author would need to reflect the changes in his project and rebuild the RBF file.

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Re: Snes on FPGA may get sof file release for de 10 nano mister

Postby NegSol » Sat Jul 28, 2018 5:36 pm

Did anyone try the SOF posted on
http://pgate1.at-ninja.jp/SNES_on_FPGA/ ... ml#release

There is an English instruction txt file . Apparently only two buttons are enabled (Start) and (A).
Maybe not worth the hassle to set up, as an SD-Card has to be prepared as well (only one rom supported?).

I sure still hope that he will release a normal working core with some rudimentary rom selection. Also a source release would help a lot the integration with MiSTer OSD... :shrug:

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Re: Snes on FPGA may get sof file release for de 10 nano mister

Postby Sorgelig » Sat Jul 28, 2018 10:02 pm

Basically, it's not for MiSTer, but for DE10-nano with I/O+SDRAM Boards.
It doesn't use any MiSTer API. And a don't see Joystick support - it's unclear how to play. Probably you won't be able to play besides pressing a single button.

This release is not worth even to try. Don't waste your time.
P.S.: i would happily help in porting this core to MiSTer if author would release the source. He would free from porting task and concentrate on core itself.

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Re: Snes on FPGA may get sof file release for de 10 nano mister

Postby AndrewSisk » Mon Sep 17, 2018 7:50 pm

this would be fun to play Jet Pilot Rising https://www.romhacking.net/homebrew/97/ it only needs A and start and is a fun game, :D to bad only VGA out, can't try,

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Re: Snes on FPGA may get sof file release for de 10 nano mister

Postby Gehstock » Mon Oct 01, 2018 8:44 am


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Re: Snes on FPGA may get sof file release for de 10 nano mister

Postby alexh » Mon Oct 01, 2018 9:40 am

The author could encrypt the HDL using the Quartus key so it can still be synthesized but no-one could edit it?

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Re: Snes on FPGA may get sof file release for de 10 nano mister

Postby ijor » Mon Oct 01, 2018 4:36 pm

Sorgelig wrote:MiSTer needs RBF file in order to load from Menu.


It is a time limited SOF? Otherwise Quartus can convert from SOF to RBF.

alexh wrote:The author could encrypt the HDL using the Quartus key so it can still be synthesized but no-one could edit it?


That is possible but it's not so easy. Altera/Intel doesn't normally provide an encryption key neither the encryption software, not even with the most expensive paid version of Quartus. And AFAIK, there is no public documentation available on the subject.

I'm not sure how exactly it is the procedure for getting the key and the tools, but I believe you must be an Altera partner and probably need to sign a special agreement. Not something that individuals can easily get.

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Re: Snes on FPGA may get sof file release for de 10 nano mister

Postby alexh » Tue Oct 02, 2018 11:08 am

ijor wrote:
alexh wrote:The author could encrypt the HDL using the Quartus key so it can still be synthesized but no-one could edit it?

That is possible but it's not so easy. Altera/Intel doesn't normally provide an encryption key neither the encryption software, not even with the most expensive paid version of Quartus.

"Quartus Prime Pro Edition" supports it. How to use it is fully documented however unlike other EDA vendor's they've not published their public key. You must request it.

Here we're Xilinx based and they have supported IEEE P1735 for years (since 2014?). With Xilinx ISE I was sure anyone could encrypt HDL and they published their public key but now it looks like for Vivado you have to request a license. (Probably a formality but I've not tried it)

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Re: Snes on FPGA may get sof file release for de 10 nano mister

Postby ijor » Sat Oct 06, 2018 1:33 pm

alexh wrote:
ijor wrote:
alexh wrote:The author could encrypt the HDL using the Quartus key so it can still be synthesized but no-one could edit it?

That is possible but it's not so easy. Altera/Intel doesn't normally provide an encryption key neither the encryption software, not even with the most expensive paid version of Quartus.

"Quartus Prime Pro Edition" supports it. How to use it is fully documented however unlike other EDA vendor's they've not published their public key. You must request it.


Seems you are right. I might have mixed up HDL encryption with encrypted IP core evaluation. But besides purchasing the expensive Pro license you still need the public key. They might not provide it to individuals and it might even require a signed NDA. Of course, it might be floating around on the net.

Here we're Xilinx based and they have supported IEEE P1735 for years (since 2014?). With Xilinx ISE I was sure anyone could encrypt HDL and they published their public key but now it looks like for Vivado you have to request a license. (Probably a formality but I've not tried it)


I assume you realize that this is not really very secure. It is mostly security by obscurity as the decryption private key must be embedded in the public software. It might have been cracked already.

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Re: Snes on FPGA may get sof file release for de 10 nano mister

Postby Sorgelig » Sat Oct 06, 2018 2:21 pm

ijor wrote:They might not provide it to individuals and it might even require a signed NDA

or they might ask you to send the source to them and they will send you back encrypted version.

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Re: Snes on FPGA may get sof file release for de 10 nano mister

Postby ijor » Sat Oct 06, 2018 2:55 pm

Sorgelig wrote:
ijor wrote:They might not provide it to individuals and it might even require a signed NDA

or they might ask you to send the source to them and they will send you back encrypted version.


And btw, HDL encryption is supported only on the Pro edition, not on the Standard one. But the Pro edition targets the high end and mid devices only. You must use the Standard edition for the low cost devices like the Cyclone families. Ergo, still no HDL encryption for our boards.

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Re: Snes on FPGA may get sof file release for de 10 nano mister

Postby alexh » Mon Oct 08, 2018 10:12 am

ijor wrote:I assume you realize that this is not really very secure. It is mostly security by obscurity as the decryption private key must be embedded in the public software. It might have been cracked already.

Wouldn't possibly know anything about that :roll:

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SNES Core WIP

Postby retrorepair » Fri Oct 26, 2018 8:09 am

How has no one mentioned this? Apparently mister support was added in July:

https://www.reddit.com/r/emulation/comm ... or_mister/

Has anyone tried it?

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Re: SNES Core WIP

Postby alexh » Fri Oct 26, 2018 8:32 am

The developer is the real deal. I've followed his work for many years. He started out with an FPGA of the sound chip. I contacted him on Twitter and brought MiSTer to his attention about a year ago and offered him an FPGA setup but never sent it to him. Looks like he got one.

http://pgate1.at-ninja.jp/SNES_on_FPGA/ ... ml#release

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Re: SNES Core WIP

Postby mattsoft » Fri Oct 26, 2018 2:25 pm

retrorepair wrote:How has no one mentioned this? Apparently mister support was added in July:

https://www.reddit.com/r/emulation/comm ... or_mister/

Has anyone tried it?


the author gets the MiSTer and DE-10 mixed up. His project is for the DE-10 and does not appear to use MiSTer.

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Re: Snes on FPGA may get sof file release for de 10 nano mister

Postby retrorepair » Sat Oct 27, 2018 11:59 am

Kinda seems like an odd mistake to make, have you tried it? I don't have one at the moment to test.

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Re: Snes on FPGA may get sof file release for de 10 nano mister

Postby PhantombrainM » Wed Nov 21, 2018 4:00 pm

I've just written to the developer about whether he's going to open his core as an open source project.

As far as I remember, he said a few years ago, he will do it as soon as someone else releases a SNES core. I reminded him and sent him the Github project and a Youtube link. Let's see what happens! ;)
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Re: Snes on FPGA may get sof file release for de 10 nano mister

Postby ijor » Wed Nov 21, 2018 4:39 pm

Is he the same developer that was asking the retro community to pay him big money to release the core as open source? Or that was somebody else?
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Re: Snes on FPGA may get sof file release for de 10 nano mister

Postby EisernSchild » Wed Nov 21, 2018 5:55 pm

ijor wrote:Is he the same developer that was asking the retro community to pay him big money to release the core as open source? Or that was somebody else?


No, that is someone else. The men you mention here wanted to start a crowdfunding campaign with the goal of $400000,- (!) to release his core open source. He claimed that releasing his code open source for free would not be "fair" to other paying customers of his firm.

Yes, we can be truly happy that srg320 released his core, he is a real sir !!

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Re: Snes on FPGA may get sof file release for de 10 nano mister

Postby PhantombrainM » Wed Nov 21, 2018 6:16 pm

ijor wrote:Is he the same developer that was asking the retro community to pay him big money to release the core as open source? Or that was somebody else?


No, not the verisnes developer.That's the one who wanted 400.000$/€.

I meant the japanese SNES On FPGA Developer: http://pgate1.at-ninja.jp/SNES_on_FPGA/ ... ml#release
He wanted to release his core when another open source one will be published.
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