furrtek wrote:About the memory size issue: how about using two 64Mx8 SDRAM chips like the IS42S86400F ? That would give 128MiB total without loading the data bus twice, also the chips aren't too expensive and would still be easy to solder. Would wiring the address/control bus in parallel require lowering the clock frequency a lot ? It may be possible to keep it at 96MHz.
8bit SDRAM will not load twice only data bus while clock, control and address will be still loaded twice. I didn't test such config. Exactly IS42S86400F won't work at required frequency as it consumes a lot 120-180mA. So, the single chip probably will work up to ~80MHz. 2 chips will be even slower. The chip i'm using consumes only 60mA.
2 chips not only load signals twice but routing will be awful in such small space (even with 4 layers) - it will additionally reduce the max clock.
There are probably some more options exist with BGA chips but i don't look at them as it's definitely not DIY friendly cases.
furrtek wrote:There's something I don't get about the occasionally long delays on the DDR3 memory. Is that caused by the embedded controler multiplexing access between the FPGA core and the ARM CPU ? If that's the case, then would it be possible to use FPGA-dedicated DDR/DDR2/DDR3 memory on the extension board ?
DDR3 is shared between many consumers. There are also refresh cycles. Nothing you can do with it besides the read with burst to the BRAM and read from BRAM at required rate. This usage implies streaming data, not random reads word by word. Although Genesis and TGfx16 work well with ROM in DDR3. For these consoles ROM is not directly accessible by video chips, so latency is not an issue for them as long as integral rate is within required pace.
I don't think DDRx is a viable option for addon. At first: it requires diff signals carefully routed which cannot be done on existing DE10-nano connectors. At second: raw DDRx control is a nightmare. Current internal DDR3 is controlled by hardware giving very simple MPFE (AvalonMM-like) interface. It won't be the same with external DDR memory.
May be it's really would be better to concentrate on NeoGeo CD and <256MBit ROMs first. Then later can think how to support larger ROMs.
I guess NeoGeo ROMs consist on separate blocks where you know which blocks are for graphics and then must go to SDRAM, Other blocks can go to DDR3. This way even some >256MBit ROMs will be supported.