yellperil wrote:slingshot wrote:Great! I'll test it. Didn't you try just to remove "enable" from the int firing logic? That way it still would not have the interrupt delayed by 2 enable cycles, and no need to use the falling edge.
No didn’t try that, I’m not that familiar with HDLs in general so I don’t know of those types of implications. Just learning as I go. Good to know though, thanks for the knowledge sharing.
Well it's not HDL speciality. Currently the code does:
....clocks...enable(flag interrupt)-clock(flag registered)...clocks...enable(flag noticed, int fired)-clock(int registered)....clocks...enable(CPU notices the int).
You can see it's 2 cycles where enable ='1' elapsed from the int fireing to the time when the CPU noticed it. Seems from your fix, this delay is too much, so there must be no enable cycle between the interrupt flagging and when the cpu notice it. If the interrupt firing is not in the enable cycle, then
enable(flag interrupt) - clock(flag registered, flag noticed, int fired)...clocks...enable(cpu notices the int)
Using the negative edge just makes two events in one cycle, which effectively doubles the clock frequency (it's ok here, but at higher frequencies this can cause timing problems).
enable(flag interrupt) - clock(flag registered)...clocks...enable negedge(flag noticed, int fired), enable posedge(cpu notices the int)
So in theory the end of both approach is the same.