Minimig (Amiga) core discussion

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Alynna
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Re: Minimig (Amiga) core discussion

Postby Alynna » Tue Jan 22, 2019 1:36 pm

So what's the official right numbers for these settings?

Also if I make the changes to the main MiSTer code to support the tap0 device, will you be able to integrate them into the mainline?

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Re: Minimig (Amiga) core discussion

Postby Sorgelig » Tue Jan 22, 2019 4:52 pm

Alynna wrote:So what's the official right numbers for these settings?

if it's about SDC, then keep it as is. At least for now.

Alynna wrote:Also if I make the changes to the main MiSTer code to support the tap0 device, will you be able to integrate them into the mainline?

I will, but only when it will be finished, i.e. when Minimig will work through this device.

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Re: Minimig (Amiga) core discussion

Postby Alynna » Tue Jan 22, 2019 5:04 pm

Sorgelig wrote:
Alynna wrote:So what's the official right numbers for these settings?

if it's about SDC, then keep it as is. At least for now.
It is about the timing thing, the setup/hold. Using 4/4 right now, should it be 4/3?

Alynna wrote:Also if I make the changes to the main MiSTer code to support the tap0 device, will you be able to integrate them into the mainline?

I will, but only when it will be finished, i.e. when Minimig will work through this device.

Thanks.

I committed new code to my repo if you want to have a look.
Some progress on the 256M board, $5xxxxxxx is filled with zeroes (which is where AmigaOS is moving the board) but is read only right now (or maybe not reading the RAM at all but at least the memory region isn't echoes of the SDRAM anymore)
I made some modifications to your genesis DDR3 verilog (so it could be instantiated multiple times at different memory regions of the DDR3), but didn't change how it works otherwise.

https://github.com/alynna/Minimig-AGA_MiSTer

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Re: Minimig (Amiga) core discussion

Postby Sorgelig » Tue Jan 22, 2019 7:53 pm

When you make commits, make sure you don't include debug data like SignalTap. You can add files into commits selectively, so you still can use *.qsf with debug while commit won't include its changes.

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Re: Minimig (Amiga) core discussion

Postby ijor » Tue Jan 22, 2019 9:44 pm

Sorgelig wrote:
Alynna wrote:So what's the official right numbers for these settings?

if it's about SDC, then keep it as is. At least for now.


If setup multicycle is 4, then hold multicycle should be 3. I can't say more generally if the multicycle constraint is correct or not, probably it is, but I'm not so familiar with the core to be sure. But regardless, the hold multicycle should (normally) be one cycle less than setup multicycle. Both setup and hold multicycle 4, almost sure is wrong.
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Re: Minimig (Amiga) core discussion

Postby slingshot » Tue Jan 22, 2019 10:39 pm

Changed to 4/3 on MiST, works well.

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Re: Minimig (Amiga) core discussion

Postby Sorgelig » Wed Jan 23, 2019 5:08 am

probably 2/1 also will work well as anything lowering down 114MHz at least twice :)

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Re: Minimig (Amiga) core discussion

Postby slingshot » Wed Jan 23, 2019 12:30 pm

Sorgelig wrote:probably 2/1 also will work well as anything lowering down 114MHz at least twice :)

It's 57 MHz effective clock then, it's about the limit of the T80. I expect TG68k is a bit more complex than that :)

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Re: Minimig (Amiga) core discussion

Postby Alynna » Wed Jan 23, 2019 7:12 pm

For those interested in these types of things, heres a little preliminary on what the ethernet will look like:

Code: Select all

// MiniMig-Net - type Zorro II - Mapping probably $E8xxxx
//             - type C64-IO   - Mapping $DFxx
//             - other cores to be determined
Offset  Size   
0000    01      (READ) Status register
                7-6:    11=24/32 bit mode, I/O buffer at offset $0100
                        10=24/32 bit mode, Pointer Buffer (PB) only
                        01=16 bit mode, Pointer buffer only
                        00=8 bit mode, byte interface only
                3:  1=RXP  New packet in progress
                2:  1=ACK  Packet / byte received by HPS
                1:  1=BSY  HPS Wait to send
                0:  1=RX   New packet sent / byte sent
0001    01      (WRITE) Control register
                7-6:    11=24/32 bit mode, I/O buffer at offset $0100
                        10=24/32 bit mode, Pointer Buffer (PB) only (PB pointer is 32bit)
                        01=16 bit mode, Pointer buffer only (PB pointer is 16bit)
                        00=8 bit mode, byte interface (send 1 byte at a time to $0F)
                2:  1=ACK   Packet / byte received by CORE
                1:  1=BSY   CORE Wait to send
                0:  1=TX    New packet ready to send / byte ready
0002    02      MTU (up to 65280) | Byte interface: ignored
0004    02      MRU (up to 65280) | Byte interface: ignored
0006    02      Pointer to PB (0000=I/O buffer)
0008    02      MSB of PB (24/32 bit mode)
000A    02      (W) Size of data at pointer buffer (R) Size of payload written to PB
000F    01      Byte Interface: Byte to send/receive
0010    F0      Reserved
-- addresses above 00FF not seen by 8 bit cores or cores with 16 bit addressing space
0100    65280   HPS mapped buffer (24/32 bit address bus only)
            Almost certainly shared with the top 64K of RTG (which won't be used)

Alot of progress been made on the 256M RAM, but, I still haven't figured out how to get the DDRAM_CLK down to tg68k.vhd where it is needed...

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Re: Minimig (Amiga) core discussion

Postby ijor » Wed Jan 23, 2019 7:20 pm

slingshot wrote:Changed to 4/3 on MiST, works well.


I see lots of timing failures (on the MiST build, didn't try MiSTer yet). Can't say if they are real or fake as a consequence of not properly constrained.

It's 57 MHz effective clock then, it's about the limit of the T80. I expect TG68k is a bit more complex than that


If they are real, then it can't even run at 28.5 MHz. Or at least it doesn't meet timing at that frequency. But the worst timing failing paths don't seem to be at the CPU core.
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Re: Minimig (Amiga) core discussion

Postby Alynna » Wed Jan 23, 2019 7:31 pm

Also I just synced to the master source and I am not sure how to resolve this conflict:

Code: Select all

<<<<<<< HEAD
   //Spare 64-bit DDR3 RAM access
   //Hooked to RTG card
   .ramclk2_clk(rtg_clk),
   .ram2_address(rtg_address),
   .ram2_burstcount(rtg_burstcount),
   .ram2_waitrequest(rtg_waitrequest),
   .ram2_readdata(rtg_readdata),
   .ram2_readdatavalid(rtg_readdatavalid),
   .ram2_read(rtg_read),
   .ram2_writedata(rtg_writedata),
   .ram2_byteenable(rtg_byteenable),
   .ram2_write(rtg_write),
=======
   //64-bit DDR3 RAM access
   .ramclk2_clk(clk_audio),
   .ram2_address(aram_address),
   .ram2_burstcount(aram_burstcount),
   .ram2_waitrequest(aram_waitrequest),
   .ram2_readdata(aram_readdata),
   .ram2_readdatavalid(aram_readdatavalid),
   .ram2_read(aram_read),
   .ram2_writedata(0),
   .ram2_byteenable(8'hFF),
   .ram2_write(0),
>>>>>>> 2de26cc65f562decf2dc3520be653534c1b06380

Any suggestions? Can I just declare a .ram3 here?

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Re: Minimig (Amiga) core discussion

Postby Sorgelig » Wed Jan 23, 2019 7:42 pm

You cannot add ram3 as there is no more free MPFE ports left.
You can remove Linux audio support while working on RTG. When you will finish RTG, i will help you to integrate Linux audio.

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Re: Minimig (Amiga) core discussion

Postby Alynna » Wed Jan 23, 2019 7:51 pm

Sorgelig wrote:You cannot add ram3 as there is no more free MPFE ports left.
You can remove Linux audio support while working on RTG. When you will finish RTG, i will help you to integrate Linux audio.

I need some help with some things is there any place I can chat you like telegram or discord?

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Re: Minimig (Amiga) core discussion

Postby Sorgelig » Wed Jan 23, 2019 8:10 pm

check your PM

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Re: Minimig (Amiga) core discussion

Postby slingshot » Thu Jan 24, 2019 10:03 am

ijor wrote:If they are real, then it can't even run at 28.5 MHz. Or at least it doesn't meet timing at that frequency. But the worst timing failing paths don't seem to be at the CPU core.

The worst paths now are in the sdram-cache controller, but it doesn't cause instabilities (at least I didn't notice it). Those are the places where the core must run in 114MHz. I don't know how a constrain can help there, probably the fitter already tried to squeeze those paths into one cycle, and failed. However the failures are mostly in the slowest device model, I think our FPGAs are not with the slowest speed rating.

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Re: Minimig (Amiga) core discussion

Postby ijor » Thu Jan 24, 2019 12:43 pm

slingshot wrote:The worst paths now are in the sdram-cache controller, but it doesn't cause instabilities (at least I didn't notice it). Those are the places where the core must run in 114MHz. I don't know how a constrain can help there, probably the fitter already tried to squeeze those paths into one cycle, and failed. However the failures are mostly in the slowest device model, I think our FPGAs are not with the slowest speed rating.


It might work for you, it might even work for most people, but it might fail for others. Might also fail only on some specific circumstances which you are not happening to test. That's precisely the reason that static timing analysis is performed.

My MiST and probably most of them, have the slowest device speed grade (-8). Of course, not all devices within the same speed grade are the same. Some will be closer to the faster grade (-7) than others. But more important, devices are not perfectly even in terms of speed. Some specific elements will be slower than others, and this will vary a lot on each device unit.

In first place change the compilation settings for achieving the fastest possible build:

Code: Select all

set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT EXTRA
# note that the parameter name is misleading. It applies to Cyclone III family as well
set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"


This will improve timing significantly. Compilation time will increase, of course. You still get timing failures but it is much better. For full timing closure you might need to implement some functional optimizations. Probably adding some pipelining.
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Re: Minimig (Amiga) core discussion

Postby slingshot » Thu Jan 24, 2019 1:56 pm

ijor wrote:

This will improve timing significantly. Compilation time will increase, of course. You still get timing failures but it is much better. For full timing closure you might need to implement some functional optimizations. Probably adding some pipelining.


Yeah, just I don't use them during development, they make the synthesis super-slow. Actually the Genesis core has bigger slacks (in the wrong direction), nobody complained yet. And compared to the latest released state back in 2017, these timing values are wonder :) Of course would be good to improve, just the sdram cache part is not something trivial to hack on.

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Re: Minimig (Amiga) core discussion

Postby ijor » Thu Jan 24, 2019 2:30 pm

slingshot wrote:Yeah, just I don't use them during development, they make the synthesis super-slow.


Super slow !? Seems like you never compiled something like ao486. That's slow! :) And I never run a really big compile on something like a FPGA form one of the Stratix families. More than 5 millions LE! Guess it's an overnight compile? :)
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Re: Minimig (Amiga) core discussion

Postby slingshot » Thu Jan 24, 2019 2:45 pm

ijor wrote:
slingshot wrote:Yeah, just I don't use them during development, they make the synthesis super-slow.


Super slow !? Seems like you never compiled something like ao486. That's slow! :) And I never run a really big compile on something like a FPGA form one of the Stratix families. More than 5 millions LE! Guess it's an overnight compile? :)


It should be like what I read about the 60-es, making punch cards and feed them to the reader :)

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Re: Minimig (Amiga) core discussion

Postby BlockABoots » Sat Jan 26, 2019 1:55 pm

Ive asked this before but never got a response, so not sure if its possible. Can you get this core to fill the whole displays height as a lot of games seem to just has a smaller display in the centre of the screen, is there no way to zoom or stretch then image?

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Re: Minimig (Amiga) core discussion

Postby Sorgelig » Sat Jan 26, 2019 4:40 pm

Manual video adjustment is implemented in Minimig.
There is no 100% automatic screen adjust as Amiga has no exact HBlank parameter.

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Re: Minimig (Amiga) core discussion

Postby remowilliams » Sat Jan 26, 2019 5:57 pm

Sorgelig wrote:Manual video adjustment is implemented in Minimig.
There is no 100% automatic screen adjust as Amiga has no exact HBlank parameter.


Would it be possible to have a set of video adjustments that could be saved/loaded independently of the main minimig configs? That could be something quite handy if possible.

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Re: Minimig (Amiga) core discussion

Postby Sorgelig » Sat Jan 26, 2019 7:07 pm

Positions are saved according to video modes with up to 64 modes can be saved. It has no relation to minimig configs.

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Re: Minimig (Amiga) core discussion

Postby remowilliams » Sat Jan 26, 2019 7:56 pm

Sorgelig wrote:Positions are saved according to video modes with up to 64 modes can be saved. It has no relation to minimig configs.


Ah, thank you. I didn't know it was that granular.

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Re: Minimig (Amiga) core discussion

Postby Alynna » Sun Jan 27, 2019 9:36 am

I think I will have the 256M RAM expansion done soon. I have also been coding the infrastructure around RTG RAM wise since its based on the same code (its just another RAM instantiation)


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