Minimig (Amiga) core discussion

https://github.com/MiSTer-devel/Main_MiSTer/wiki

Moderators: Mug UK, Zorro 2, Greenious, spiny, Sorgelig, Moderator Team

slingshot
Atari God
Atari God
Posts: 1048
Joined: Mon Aug 06, 2018 3:05 pm

Re: Minimig (Amiga) core discussion

Postby slingshot » Sat Jan 19, 2019 1:57 pm

The biggest problem with minimig is that the TG68k runs on 114 MHz. This needs to be constrained in the SDC with some multicycle paths, since it's impossible to have such high clock for the CPU.
This one did the job on MiST:
set_multicycle_path -from {TG68K:tg68k|TG68KdotC_Kernel:pf68K_Kernel_inst|*} -setup 4
set_multicycle_path -from {TG68K:tg68k|TG68KdotC_Kernel:pf68K_Kernel_inst|*} -hold 4

With some other changes, it's quite stable. Will upload to github if you're interested.

Sorgelig
Fuji Shaped Bastard
Fuji Shaped Bastard
Posts: 4881
Joined: Mon Dec 14, 2015 10:51 am
Location: Russia/Taiwan

Re: Minimig (Amiga) core discussion

Postby Sorgelig » Sat Jan 19, 2019 2:06 pm

slingshot wrote:The biggest problem with minimig is that the TG68k runs on 114 MHz. This needs to be constrained in the SDC with some multicycle paths, since it's impossible to have such high clock for the CPU.
This one did the job on MiST:
set_multicycle_path -from {TG68K:tg68k|TG68KdotC_Kernel:pf68K_Kernel_inst|*} -setup 4
set_multicycle_path -from {TG68K:tg68k|TG68KdotC_Kernel:pf68K_Kernel_inst|*} -hold 4

With some other changes, it's quite stable. Will upload to github if you're interested.

Of course interested. Although, what is stable on Cyclone III might be still unstable on Cyclone V.

User avatar
Alynna
Atari freak
Atari freak
Posts: 57
Joined: Tue Sep 18, 2018 5:54 pm

Re: Minimig (Amiga) core discussion

Postby Alynna » Sat Jan 19, 2019 2:13 pm

Sorgelig wrote:You've made things only worse.
The clocks you've created are called asynchronous clocks. This is worst thing you can do for clocks :)
You will see Quartus warnings about signals used as clocks without declaration.
You may describe these clocks in SDC file, so Quartus won't complain. But it is great source of instabilities.


But isn't this exactly how the 7mhz signal is generated right there in amiga_clk.v?

User avatar
Alynna
Atari freak
Atari freak
Posts: 57
Joined: Tue Sep 18, 2018 5:54 pm

Re: Minimig (Amiga) core discussion

Postby Alynna » Sat Jan 19, 2019 2:19 pm

yes i am very interested please upload to github

Sorgelig
Fuji Shaped Bastard
Fuji Shaped Bastard
Posts: 4881
Joined: Mon Dec 14, 2015 10:51 am
Location: Russia/Taiwan

Re: Minimig (Amiga) core discussion

Postby Sorgelig » Sat Jan 19, 2019 2:22 pm

Alynna wrote:But isn't this exactly how the 7mhz signal is generated right there in amiga_clk.v?

yes, it is. See the comment there:

Code: Select all

  output wire           clk_7,      // 7MHz  output clock (  7.171875MHz) DO NOT USE IT AS A CLOCK!

It's not used as clock but as reference signal in some places.

User avatar
Alynna
Atari freak
Atari freak
Posts: 57
Joined: Tue Sep 18, 2018 5:54 pm

Re: Minimig (Amiga) core discussion

Postby Alynna » Sat Jan 19, 2019 2:24 pm

though I think I can sync both the 28 and 7 mhz clock by deriving them both from the SDRAM clock and dividing the 114/4 to 28 and the 114/16=7.16. Since they will be being divided at the same time.... they should be in perfect sync right?

User avatar
Alynna
Atari freak
Atari freak
Posts: 57
Joined: Tue Sep 18, 2018 5:54 pm

Re: Minimig (Amiga) core discussion

Postby Alynna » Sat Jan 19, 2019 3:11 pm

Sorgelig wrote:
slingshot wrote:The biggest problem with minimig is that the TG68k runs on 114 MHz. This needs to be constrained in the SDC with some multicycle paths, since it's impossible to have such high clock for the CPU.
This one did the job on MiST:
set_multicycle_path -from {TG68K:tg68k|TG68KdotC_Kernel:pf68K_Kernel_inst|*} -setup 4
set_multicycle_path -from {TG68K:tg68k|TG68KdotC_Kernel:pf68K_Kernel_inst|*} -hold 4

With some other changes, it's quite stable. Will upload to github if you're interested.

Of course interested. Although, what is stable on Cyclone III might be still unstable on Cyclone V.


Where do I put these lines?

Sorgelig
Fuji Shaped Bastard
Fuji Shaped Bastard
Posts: 4881
Joined: Mon Dec 14, 2015 10:51 am
Location: Russia/Taiwan

Re: Minimig (Amiga) core discussion

Postby Sorgelig » Sat Jan 19, 2019 3:14 pm

Alynna wrote:though I think I can sync both the 28 and 7 mhz clock by deriving them both from the SDRAM clock and dividing the 114/4 to 28 and the 114/16=7.16. Since they will be being divided at the same time.... they should be in perfect sync right?


pull latest changes from my repo. It fixes instability. Basically it's slingshot's solution posted above (with adjust to MiSTer code).

slingshot
Atari God
Atari God
Posts: 1048
Joined: Mon Aug 06, 2018 3:05 pm

Re: Minimig (Amiga) core discussion

Postby slingshot » Sat Jan 19, 2019 3:21 pm

Sorgelig wrote:Of course interested. Although, what is stable on Cyclone III might be still unstable on Cyclone V.


If TimeQuest mostly likes it, then it shouldn't be a difference.
This one helps on MiST:
https://github.com/gyurco/minimig-mist/ ... 90d57a329b

User avatar
Alynna
Atari freak
Atari freak
Posts: 57
Joined: Tue Sep 18, 2018 5:54 pm

Re: Minimig (Amiga) core discussion

Postby Alynna » Sat Jan 19, 2019 3:59 pm

thanks and thanks for your patience with my stupid n00b questions and ideas. I am trying to learn this.

Sorgelig
Fuji Shaped Bastard
Fuji Shaped Bastard
Posts: 4881
Joined: Mon Dec 14, 2015 10:51 am
Location: Russia/Taiwan

Re: Minimig (Amiga) core discussion

Postby Sorgelig » Sat Jan 19, 2019 4:21 pm

slingshot wrote:
Sorgelig wrote:Of course interested. Although, what is stable on Cyclone III might be still unstable on Cyclone V.


If TimeQuest mostly likes it, then it shouldn't be a difference.
This one helps on MiST:
https://github.com/gyurco/minimig-mist/ ... 90d57a329b


Code: Select all

set_multicycle_path -from [get_clocks {amiga_clk|amiga_clk_i|altpll_component|auto_generated|pll1|clk[2]}] -to [get_clocks {amiga_clk|amiga_clk_i|altpll_component|auto_generated|pll1|clk[1]}] -setup 4
set_multicycle_path -from [get_clocks {amiga_clk|amiga_clk_i|altpll_component|auto_generated|pll1|clk[2]}] -to [get_clocks {amiga_clk|amiga_clk_i|altpll_component|auto_generated|pll1|clk[1]}] -hold 4

I think doing this between PLL outputs is unneeded. PLL outputs usually are constrained by Quartus itself. That's why we don't need to describe clocks coming from PLL.

slingshot
Atari God
Atari God
Posts: 1048
Joined: Mon Aug 06, 2018 3:05 pm

Re: Minimig (Amiga) core discussion

Postby slingshot » Sat Jan 19, 2019 4:28 pm

Sorgelig wrote:

Code: Select all

set_multicycle_path -from [get_clocks {amiga_clk|amiga_clk_i|altpll_component|auto_generated|pll1|clk[2]}] -to [get_clocks {amiga_clk|amiga_clk_i|altpll_component|auto_generated|pll1|clk[1]}] -setup 4
set_multicycle_path -from [get_clocks {amiga_clk|amiga_clk_i|altpll_component|auto_generated|pll1|clk[2]}] -to [get_clocks {amiga_clk|amiga_clk_i|altpll_component|auto_generated|pll1|clk[1]}] -hold 4

I think doing this between PLL outputs is unneeded. PLL outputs usually are constrained by Quartus itself. That's why we don't need to describe clocks coming from PLL.


Maybe newer Quartus can handle it, but in 13.1, I always see problems in the reports if there's a worst case when a path cannot work in a 1-cycle transition between clocks (even if they're in sync, just one is an exact multiple of the other).

slingshot
Atari God
Atari God
Posts: 1048
Joined: Mon Aug 06, 2018 3:05 pm

Re: Minimig (Amiga) core discussion

Postby slingshot » Sat Jan 19, 2019 4:48 pm

Btw any news on a fixed 68020?

User avatar
Alynna
Atari freak
Atari freak
Posts: 57
Joined: Tue Sep 18, 2018 5:54 pm

Re: Minimig (Amiga) core discussion

Postby Alynna » Sat Jan 19, 2019 6:22 pm

OBTW on the HPS side could we please get a tap0 network device bridged to the main ethernet device? I am planning on adding network support. This will be useful on all cores.

It will probably need the linux bridging package, and maybe a kernel config change.

If this is already supported never mind me (but I didn't see brctl installed)

Sorgelig
Fuji Shaped Bastard
Fuji Shaped Bastard
Posts: 4881
Joined: Mon Dec 14, 2015 10:51 am
Location: Russia/Taiwan

Re: Minimig (Amiga) core discussion

Postby Sorgelig » Sat Jan 19, 2019 7:35 pm

I think you need to be get familiar with Minimig code, so you will understand how it communicates with user and HPS. I have no idea what is tap0. If it's Amiga network device then it must be implemented in the core first. You need to decide abstraction layer and add bridges on both FPGA and HPS side.
Currently only internet through UART is implemented in Minimig. It's not fast but works.

User avatar
Alynna
Atari freak
Atari freak
Posts: 57
Joined: Tue Sep 18, 2018 5:54 pm

Re: Minimig (Amiga) core discussion

Postby Alynna » Sat Jan 19, 2019 9:05 pm

A tap device is a linux virtual ethernet device.
You can make them with the command: ip tuntap add mode tap tap0
And remove likewise: ip tuntap del tap0

When it is made, then Linux creates a device file like /dev/tun/tap0
and also an ethernet adapter is made "tap0"

You can then open the device /dev/tun/tap0 and send layer 2 ethernet frames to it (and get them from it) through a file descriptor.
If this is available to a core, then the core just needs to open this file (through the HPS) and send and receive packets through it.
The piece of (simulated) hardware on the core side would be implemented however is needed (like you could make an NE2000 for DOS, RRNET MK3 for C64, A2065 for Amiga, etc) and use the tap to move packets through it.

Furthermore, if tap0 is bridged to eth0, then the packets will go through the ethernet to the rest of the network and the core will look like it is ON the same network as HPS :)

(PS: Already using the PPP device. It certainly works, but when I go to make RTG, i'm planning on writing the RTG's ROM on an Amiga 1000 with a vampire on it and i'd like to be able to copy that ROM over to Minimig quickly as needed for testing :) Networking is actually my next priority after the RAM expansion device. Which is almost done, just have to figure out how i'm hooking up the DDR3)

witchmaster
Atari maniac
Atari maniac
Posts: 83
Joined: Wed Jun 15, 2011 10:50 am

Re: Minimig (Amiga) core discussion

Postby witchmaster » Sun Jan 20, 2019 9:29 am

Nice to see that somebody is doing further development on the Amiga core. Thanks Alynna, keep up the good work! :)

bitfan2011
Obsessive compulsive Atari behavior
Obsessive compulsive Atari behavior
Posts: 110
Joined: Sat Dec 29, 2018 5:46 pm

Re: Minimig (Amiga) core discussion

Postby bitfan2011 » Sun Jan 20, 2019 11:51 am

love this core, please keep up the fine work

what is the "safest" configuration which should run the majority of HDF files i attach? i never even used an amiga before emulation arrived.

fille1976
Retro freak
Retro freak
Posts: 15
Joined: Sat Nov 17, 2018 4:33 pm

Re: Minimig (Amiga) core discussion

Postby fille1976 » Sun Jan 20, 2019 3:07 pm

Just updated via script update minimig,banshee cd32 is unplayable,something is wrong with the controls in the game.
Can someone test this?,i knew it worked before with some earlier rev of the core.

ijor
Hardware Guru
Hardware Guru
Posts: 3792
Joined: Sat May 29, 2004 7:52 pm
Contact:

Re: Minimig (Amiga) core discussion

Postby ijor » Sun Jan 20, 2019 6:50 pm

slingshot wrote:The biggest problem with minimig is that the TG68k runs on 114 MHz. This needs to be constrained in the SDC with some multicycle paths, since it's impossible to have such high clock for the CPU.
This one did the job on MiST:
set_multicycle_path -from {TG68K:tg68k|TG68KdotC_Kernel:pf68K_Kernel_inst|*} -setup 4
set_multicycle_path -from {TG68K:tg68k|TG68KdotC_Kernel:pf68K_Kernel_inst|*} -hold 4


This is probably wrong. Normally you don't use the same number of cycles for both setup and hold. Check with TimeQuest GUI if you are not sure.
Fx Cast: Atari St cycle accurate fpga core

slingshot
Atari God
Atari God
Posts: 1048
Joined: Mon Aug 06, 2018 3:05 pm

Re: Minimig (Amiga) core discussion

Postby slingshot » Mon Jan 21, 2019 9:19 am

ijor wrote:
slingshot wrote:The biggest problem with minimig is that the TG68k runs on 114 MHz. This needs to be constrained in the SDC with some multicycle paths, since it's impossible to have such high clock for the CPU.
This one did the job on MiST:
set_multicycle_path -from {TG68K:tg68k|TG68KdotC_Kernel:pf68K_Kernel_inst|*} -setup 4
set_multicycle_path -from {TG68K:tg68k|TG68KdotC_Kernel:pf68K_Kernel_inst|*} -hold 4


This is probably wrong. Normally you don't use the same number of cycles for both setup and hold. Check with TimeQuest GUI if you are not sure.


Didn't experience problems with it, also TimeQuest like it. The idea here only to tell the TG68K kernel that it can safely "skip" 4 cycles, like if it would get an 1/4 clock. Better fix would be to really give it the 28MHz clock instead of the 112, but many signals, even the enable are created in the 112 MHz domain, so it would be tricky.

ijor
Hardware Guru
Hardware Guru
Posts: 3792
Joined: Sat May 29, 2004 7:52 pm
Contact:

Re: Minimig (Amiga) core discussion

Postby ijor » Mon Jan 21, 2019 1:42 pm

slingshot wrote:
ijor wrote:
slingshot wrote:set_multicycle_path -from {TG68K:tg68k|TG68KdotC_Kernel:pf68K_Kernel_inst|*} -setup 4
set_multicycle_path -from {TG68K:tg68k|TG68KdotC_Kernel:pf68K_Kernel_inst|*} -hold 4


This is probably wrong. Normally you don't use the same number of cycles for both setup and hold. Check with TimeQuest GUI if you are not sure.


Didn't experience problems with it, also TimeQuest like it. The idea here only to tell the TG68K kernel that it can safely "skip" 4 cycles, like if it would get an 1/4 clock.


Just because TimeQuest doesn't complain it doesn't mean it's correct. I know exactly what was the intention of these constraints. But the second line, the one with the "hold" parameter can't be right. You can "skip" 4 cycles for setup purposes, but not for hold. I meant to check it with TimeQuest GUI, not with the TimeQuest analyzer. Check your hold slack on those nodes and you would probably see it doesn't make much sense.

The normal setup and hold relationships are 1 and 0 respectively. In cases like this, that you apply a multicycle because you are using a clock enable as a clock divisor, you probably still want to preserve the relation between setup and hold. So you probably need "-hold 3", and not "-hold 4". Again, the best way to understand and visualize this is with TimeQuest GUI.
Fx Cast: Atari St cycle accurate fpga core

slingshot
Atari God
Atari God
Posts: 1048
Joined: Mon Aug 06, 2018 3:05 pm

Re: Minimig (Amiga) core discussion

Postby slingshot » Mon Jan 21, 2019 2:35 pm

Ah, ok, I wasn't aware of the base is 1/0, I assumed 1/1. Will check.

NegSol
Captain Atari
Captain Atari
Posts: 321
Joined: Sat Dec 05, 2015 9:22 pm

Re: Minimig (Amiga) core discussion

Postby NegSol » Mon Jan 21, 2019 7:43 pm

How does one change the info on the different config files in the OSD for this core? All configuration entries now look the the same. Before there were numbers. Do I have to manually edit the minimigX.cfg files? Which bytes to edit? :shrug:

Sorgelig
Fuji Shaped Bastard
Fuji Shaped Bastard
Posts: 4881
Joined: Mon Dec 14, 2015 10:51 am
Location: Russia/Taiwan

Re: Minimig (Amiga) core discussion

Postby Sorgelig » Mon Jan 21, 2019 9:21 pm

NegSol wrote:How does one change the info on the different config files in the OSD for this core? All configuration entries now look the the same. Before there were numbers. Do I have to manually edit the minimigX.cfg files? Which bytes to edit? :shrug:

just load the config and then save it back. The config display info is written upon save.


Return to “MiSTer”

Who is online

Users browsing this forum: No registered users and 3 guests