MISTer on DE0-nano-SoCKit?

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olin
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Re: MISTer on DE0-nano-SoCKit?

Postby olin » Wed Dec 13, 2017 1:48 pm

Yesterday I built 2 SDRAM boards, none of them was working. Both were using the 16MByte ISSI chips marked with speed 7 (144 MHz). The first one was soldered by hand, second one via reflow on my inverted cloth iron (checked the temperature was 220°C via thermocouple). I tested those SDRAM boards on modified memory tester that checks only 16MBytes on 114MHz. Both chips produced tons of errors, then double-checked solder joints with the same result. Both chips were brand new, but contained a sticker mentioned that chips need to be pre-baked according to J-STD-033C. Checked the document and they state once the package seal of the chip is opened, the chip immediately absorb moisture from the air. If you then try to reflow such moisturised chip on 220°C or higher the moisture trapped inside will pop inside causing micro fractures and damages the chip. These internal cracks are only visible via X-ray. Bummer... They recommend to bake the chip before reflow for 8 hours on 120°C or for 4 hours on 150°C. Well, I'll try to pre-bake the chips next time, will report the results.. :)

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Re: MISTer on DE0-nano?

Postby Sorgelig » Wed Dec 13, 2017 2:49 pm

OMG :) Never met such problems :)
I simply solder SDRAM with my simple soldering iron. I don't pre-bake anything.
I don't think DE0-nano has better electrical characteristics of GPIO than DE10-nano. Thus, if you want to get SDRAM with acceptable speed you need to use SDRAM chip listed on Wiki. Any other chip will be worse.

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Re: MISTer on DE0-nano?

Postby ijor » Wed Dec 13, 2017 2:56 pm

olin wrote:Yesterday I built 2 SDRAM boards, none of them was working. Both were using the 16MByte ISSI chips marked with speed 7 (144 MHz). The first one was soldered by hand, second one via reflow on my inverted cloth iron (checked the temperature was 220°C via thermocouple). I tested those SDRAM boards on modified memory tester that checks only 16MBytes on 114MHz. Both chips produced tons of errors, then double-checked solder joints with the same result. ...


I wouldn't waste too much time with soldering issues before testing the Alliance Memory -6 part and see if that makes a big difference. And once again, the other thing that might make a significant difference is using a dedicated clock output pin. But that depends on being present in the DE0 GPIO port and being located in a more or less convenient pin at the connector. Plus, it probably would require adjusting the PLL shift.

Also, are you using a heat sink and a cooler? May be you need it even more than the DE10.

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Re: MISTer on DE0-nano?

Postby ijor » Wed Dec 13, 2017 4:15 pm

I checked the schematics. The DE0 does have PLL dedicated output pins at GPIO pins GPIO_0_D14 and GPIO_0_D15. If you decide to explore that option and need help adjusting the PLL, let me know.

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Re: MISTer on DE0-nano?

Postby olin » Thu Dec 14, 2017 12:35 am

Another test, this time AMIC A43L3616AV-7F, 16 MBytes in 4 banks as well. No luck either - the same issue as the others (multitude of errors right from the beginning). I think I'm 'cured' from trying different SDRAM chips :) I didn't order Alliance chip in the first place because RS_online doesn't sell it, ordering from Digikey or Mouser seemed to be too much of a hassle of registering new account just for this (plus ridiculous postage for small orders). But I'll do it if there is no other reasonable option.

Also, are you using a heat sink and a cooler? May be you need it even more than the DE10.

I use passive heat sink on the the SoC and now added a small copper heat sink on Winbond (w9825g6jh-6) SDRAM - which helped. On 114MHz no error, on 166MHz the first error occurs when reaching 0xA20 green counter. I can't set other PLL frequencies as they are not in git and I don't know how to regenerate them yet (will have to look for some tutorials).

The DE0 does have PLL dedicated output pins at GPIO pins GPIO_0_D14 and GPIO_0_D15. If you decide to explore that option and need help adjusting the PLL, let me know.

If that means changing the SDRAM board layout and breaking compatibility with Sorgelig's SDRAM board - then it would be the last resort. I'll try Alliance Memory SDRAM first and then decide. Thanks for the offer.

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Re: MISTer on DE0-nano?

Postby ijor » Thu Dec 14, 2017 2:35 am

olin wrote:I use passive heat sink on the the SoC and now added a small copper heat sink on Winbond (w9825g6jh-6) SDRAM - which helped.


So it seems heat is a major issue. You might need a fan, and not just a passive heat sink.

If that means changing the SDRAM board layout and breaking compatibility with Sorgelig's SDRAM board - then it would be the last resort.


Yes, you must change at least a couple of pins. But why do you care? I thought you decided for a unified DRAM and I/O board combined, that is not backwards compatible anyway. Or am I missing something? But I agree that this doesn't seem to be the top priority right now.

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Re: MISTer on DE0-nano?

Postby olin » Fri Dec 15, 2017 7:48 pm

ijor wrote:So it seems heat is a major issue. You might need a fan, and not just a passive heat sink.

Yes, heat is definitely an issue, a small fan that fits the mounting holes on the board is on the way, but I suspect it will take time to arrive (christmas holidays slowing down deliveries).

ijor wrote:Yes, you must change at least a couple of pins. But why do you care? I thought you decided for a unified DRAM and I/O board combined, that is not backwards compatible anyway. Or am I missing something? But I agree that this doesn't seem to be the top priority right now.

Well, unified board is still the plan, but if it turns out the heat is too much of a problem because SDRAM is currently positioned on top of the FPGA chip (which is the heat producer) I might change the design. Remember this is still an experiment - I started like 4 weeks ago. Also there was the idea about making 'Super simple DIY' basic IO board with VGA and audio only - possibly through hole components. In such case compatibility with existing SDRAM boards would be a big advantage. I'm afraid deviating from the DE10 design would make it less simple to port cores, therefore it would detract interest. And I prefer to make things as simpler as possible - as long as they work. Let's see, I'll order the exact Alliance memory chips, mount a heat sink, test it and then decide what to do next.

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Re: MISTer on DE0-nano?

Postby ijor » Sat Dec 16, 2017 12:55 pm

olin wrote:I'm afraid deviating from the DE10 design would make it less simple to port cores, therefore it would detract interest.


I don't think it will make porting cores less simple. Why you think it will? What you loose is the possibility of using DE-10 DRAM boards. That's why I am saying that it depends on using an unified board design or not. But again, I agree, heat and the exact DRAM chip part are much more important so far.

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Re: MISTer on DE0-nano?

Postby olin » Sat Dec 16, 2017 7:10 pm

ijor wrote:I don't think it will make porting cores less simple. Why you think it will?

I was under impression that PLL shift and other related changes would require modification of sys/pll.qip and pll.v. If not then great, if yes then I don't have enough knowledge about Quartus to judge how easy/hard is to make such changes dependent upon selected 'Revision', and whether the changes would be possibly accepted upstream in cores.

Right now the porting to de0ns is fairly simple, also the changes in the project sources are 'non-invasive'. It involves copying the Lite Revision into separate de0ns revision, remapping pins, chip name, temperature restrictions and removing HDMI pins in the new de0ns*.qsf. Then enabling a new NO_HDMI macro in the settings (of the new Revision) and adding NO_HDMI `ifndefs at 3 places in sys_top.v . At that point hitting Ctrl+L will produce the final product - <core>.rbf. Simple as that. Remapping of the pins from de10 to de0ns is done by a tool, so it's just a matter of few seconds, no hassle or error-prone.

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Re: MISTer on DE0-nano?

Postby ijor » Sun Dec 17, 2017 2:10 am

olin wrote:I was under impression that PLL shift and other related changes would require modification of sys/pll.qip and pll.v. If not then great, if yes then I don't have enough knowledge about Quartus to judge how easy/hard is to make such changes dependent upon selected 'Revision', and whether the changes would be possibly accepted upstream in cores.


You might need to modify the PLL shift and that would involve changing the associated PLL files, of course. Can't say for sure without performing a timing analysis. But the truth is that you should do it anyway for getting optimal performance. That also depends a lot on the frequency of the DRAM clock used by the specific core.

Changing PLL parameters is pretty trivial if you are familiar with Quartus. What might be not so trivial is to find the optimal shift phase.

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Re: MISTer on DE0-nano?

Postby Sorgelig » Sun Dec 17, 2017 4:50 am

Shift the phase is the easiest thing to do. But first, you need to finish the HW design. At least you need to fix the pin assignment.
Shift amount should be done on max supposed to be supported frequency. For example on 167MHz. Lower frequencies will use the same phase shift. Just shift it a little and see how many errors you have. With iterations you will find the right amount of shift.

I agree it's much better to use the same pin assignment as on DE10-nano SDRAM board. I mean, same positions of signals on SDRAM board. DE0-nano pin assignment will be different of course.
In this case, DE0-nano users will be able to buy the same SDRAM board as DE10-nano users. Having incompatible DE0-nano SDRAM board will give less chance that you can buy an assembled board.

But, of course if other pin placements will produce much better result, then may be it's better to make a specific to DE0-nano board.

olin, you need to assemble DE10-nano SDRAM board and test it to make a decision.

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Re: MISTer on DE0-nano?

Postby ijor » Sun Dec 17, 2017 12:23 pm

Sorgelig wrote:Shift the phase is the easiest thing to do. But first, you need to finish the HW design. At least you need to fix the pin assignment.
Shift amount should be done on max supposed to be supported frequency. For example on 167MHz. Lower frequencies will use the same phase shift. Just shift it a little and see how many errors you have. With iterations you will find the right amount of shift.


Not sure that is the best method to find the optimal shift. The right way is through timing analysis. If you want, you can combine some measurements with timing analysis.

Doing just testing will make the result optimized for your particular setup, not for the average. There are significant silicon variations among different chips, even with the same speed grade. You might happen to have a rather fast one and the shift might be not enough for the normal case. Or the other way around.

The ideal shift depends also in a couple of other factors, not just the frequency. Mainly if the signals use fast I/O registers or not. As I understand the memory test use fast I/O on all the DRAM signals. The timing might be tighter on a core that doesn't, even if it uses a lower frequency.

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Re: MISTer on DE0-nano?

Postby Sorgelig » Sun Dec 17, 2017 12:35 pm

ijor wrote:Not sure that is the best method to find the optimal shift. The right way is through timing analysis. If you want, you can combine some measurements with timing analysis.

Yeah. Go measure it. Just let me find the best sit to watch ;)

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Re: MISTer on DE0-nano?

Postby ijor » Sun Dec 17, 2017 12:40 pm

Sorgelig wrote:Yeah. Go measure it. Just let me find the best sit to watch ;)


You need high end instruments. I don't have the right equipment. Then just perform timing analysis, and of course, validate it with some testing.

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Re: MISTer on DE0-nano-SoCKit?

Postby olin » Thu Dec 21, 2017 6:19 pm

Just a small update: I compiled the C64 core, NES core, both work prefectly on VGA output. I've received my Alliance Memory SDRAM chips, but will be away from my workbench so SDRAM board will have to wait few weeks. I'll try to recompile some more (probably Arcade) cores in the meantime.

BTW. thanks for changing the thread name - it was misleading before

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Re: MISTer on DE0-nano-SoCKit?

Postby olin » Sat Jan 06, 2018 9:52 pm

Today I've built 2 SDRAM boards with Alliance Memory AS4C16M16SA-6TCN chip. None of them work. Both produce significant amount of errors on 114 MHz memtest (board 1 - about 0x10000 errors, board 2 - about 0x36000 errors during 0x100 iterations). I have triple checked the soldering of the chip (with my cheap microscope) that there is no short between the pins, also checked the pads are soldered to IC pins. I also reheated the socket pins solder joints to make sure the is no cold joint. My thoughts about possible reasons:

1) I really suck at soldering :), this could indeed be true.
2) I got a less tolerant batch of Alliance memory chips.
3) My SDRAM design is not optimal (why does it work OK with Winbond chip then?)
4) Other reason or combination of above.

Next to try:
1) Order and build Sorgelig's SDRAM board
2) Buy soldered SDRAM board that has been tested and verified.
3) Find out whether the errors occur at random addresses or they begin at specific address (to get a hint which address/data bit may cause the issues)
4) Buy another Winbond chip (ideally the same type I already have) and try whether I get better results than Alliance chip (or my Winbond SDRAM board is just a lucky coincidence).

Edit:
here are actual snapshots of few pads by using my microscope - just for an illustration. The solder joints are not super-clean, but IMHO I'd expect them to work - or am I too optimistic? Let me know if this is a crap :)
You do not have the required permissions to view the files attached to this post.

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Re: MISTer on DE0-nano-SoCKit?

Postby Sorgelig » Sun Jan 07, 2018 12:13 am

1) different traces length. Clock trace is highly sensitive to length and position. Shorter you will make it - better result will get.
2) different length and interference inside the DE0 board.

You can compensate the delays in SDC file, but it's a bit tricky.
I suggest to try my version of SDRAM board to see how good it will work.

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Re: MISTer on DE0-nano-SoCKit?

Postby alfishe » Sun Jan 07, 2018 7:32 am

olin wrote:1) I really suck at soldering :), this could indeed be true.


Soldering quality has no influence (as long as you have no bridges or cold joints). But flux residue might do bad things. Give your board alcohol bath =)
But... board design is the key here. Alliance chips guarantee at least 140MHz with sorgelig boards.

I wish we had anyone capable to simulate EM design in our community. Per measurements boards are suffer from overshoot/ringing but have no idea if it's possible to make it better or sorgelig just achieved the limit. Or it's possible to apply scientific approach and get probably 4 layer board but with much better signal characteristics.

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Re: MISTer on DE0-nano-SoCKit?

Postby olin » Sun Jan 07, 2018 1:30 pm

Success! I decided to try my boards on some low speed frequency to check whether they work on electrical level (eliminate possibility of soldering issues). I had to find out how to change PLL. Fortunately it was quite easy: in memtest project switch to "IP Components" in Navigator, then right click on 'pll' Entity and then select "Edit in Parameter editor" option. So I generated different version of memtest between 80MHz - 150MHz in 10MHz steps, using the phase shift value of -4350ps as set in the latest memtest code. The SDRAM board run OK even on 150MHz (so far did only short term test ~5 minutes, 0 errors)

The issue in my case was that I previously compiled 114MHz version of the metest by using an old code that has the PLL phase shift set to -60 degrees (which by my calculations is about -1463ps). The value doesn't work with the combination of my SDRAM board and Alliance Memory chip. Surprisingly it works with the Winbond chip so I wonder whether the Winbond might be slightly more tolerant to timing. To verify this assumption I generated another memtest version with 120MHz and -1463ps phase shift and indeed the test failed miserably (similar amount of errors as seen previously) with Alliance chip, but OK with Winbond chip(!)

The positive thing on this exercise is that now I have different memtest speed versions and have more options to test SDRAM boards. I also learned how to check and change PLL in Quartus. Before I compile a new core I might check the PLL and verify the phase shift value is compatible.
I'm going to do longer tests, but so far it looks my SDRAM board with Alliance chip and DE0-ns works fine.

Thanks for all suggestions.
Last edited by olin on Sun Jan 07, 2018 2:47 pm, edited 1 time in total.

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Re: MISTer on DE0-nano-SoCKit?

Postby Sorgelig » Sun Jan 07, 2018 2:36 pm

alfishe wrote:Or it's possible to apply scientific approach and get probably 4 layer board but with much better signal characteristics.

i've tried 4 layers design and found no differences from 2 layers.

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Re: MISTer on DE0-nano-SoCKit?

Postby alfishe » Sun Jan 07, 2018 6:04 pm

Sorgelig wrote:i've tried 4 layers design and found no differences from 2 layers.


By scientific approach I ment to use specialized software like https://www.cst.com/products/cstpcbs to check violations for common rules (current return paths, termination) as well as more complex simulation.

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Re: MISTer on DE0-nano-SoCKit?

Postby alfishe » Sun Jan 07, 2018 6:14 pm

olin wrote:So I generated different version of memtest between 80MHz - 150MHz in 10MHz steps, using the phase shift value of -4350ps as set in the latest memtest code. The SDRAM board run OK even on 150MHz (so far did only short term test ~5 minutes, 0 errors)


Congratulations!

Out of curiosity - could you please describe (or point me to some tutorial) how to calculate PLL phase shifts and so one. Tried to go through altera tutorials on TimeQuest - didn't find any practical benefit yet.

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Re: MISTer on DE0-nano-SoCKit?

Postby Sorgelig » Sun Jan 07, 2018 7:00 pm

The real calculation is too complex to calculate. It's pure practical trials on real HW.

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Re: MISTer on DE0-nano-SoCKit?

Postby ijor » Sun Jan 07, 2018 7:22 pm

alfishe wrote:Out of curiosity - could you please describe (or point me to some tutorial) how to calculate PLL phase shifts and so one. Tried to go through altera tutorials on TimeQuest - didn't find any practical benefit yet.


Just calculate the center of the waveform's eye:

- Compile the core without any PLL shift and with the relevant I/O delays disabled.

- Make sure you have the right constrains on your SDC file.

- Run Timequest and check your worst case Setup time and Hold time slack for the relevant signals. You normally have a fair amount of Setup slack to spare, and too little or negative hold slack.

- The ideal PLL shift in time units should be the one that would give the same value for the Setup slack and the Hold slack. So it's as simple as (SetupSlackWithNoShift-HoldSlackWithNoShift)/2

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Re: MISTer on DE0-nano-SoCKit?

Postby olin » Mon Jan 08, 2018 7:49 pm

Just an update, I was able to run the SDRAM on 150MHz for more than 3 hours with 0 errors, then gave up. I also connected a heat sink and a fan (Sunon MC25100V2-000U-A99, Vapo-Bearing, 16.0dB). I found out the fan works when powered by 3.3V (spec. is 5V) with lower RPM (although it is not advertised feature) so it is more silent. To power it by 3.3V I used P4 connector pin 1 and 2, but I plan to update the IO board and make an alternative fan connector for 3.3V. On touch the heat-sink is slightly warm (under load for ~ 40 minutes), my thermocouple displayed ~32 deg.C which should be OK.


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