olin wrote:Yesterday I built 2 SDRAM boards, none of them was working. Both were using the 16MByte ISSI chips marked with speed 7 (144 MHz). The first one was soldered by hand, second one via reflow on my inverted cloth iron (checked the temperature was 220°C via thermocouple). I tested those SDRAM boards on modified memory tester that checks only 16MBytes on 114MHz. Both chips produced tons of errors, then double-checked solder joints with the same result. ...
Also, are you using a heat sink and a cooler? May be you need it even more than the DE10.
The DE0 does have PLL dedicated output pins at GPIO pins GPIO_0_D14 and GPIO_0_D15. If you decide to explore that option and need help adjusting the PLL, let me know.
olin wrote:I use passive heat sink on the the SoC and now added a small copper heat sink on Winbond (w9825g6jh-6) SDRAM - which helped.
If that means changing the SDRAM board layout and breaking compatibility with Sorgelig's SDRAM board - then it would be the last resort.
ijor wrote:So it seems heat is a major issue. You might need a fan, and not just a passive heat sink.
ijor wrote:Yes, you must change at least a couple of pins. But why do you care? I thought you decided for a unified DRAM and I/O board combined, that is not backwards compatible anyway. Or am I missing something? But I agree that this doesn't seem to be the top priority right now.
olin wrote:I'm afraid deviating from the DE10 design would make it less simple to port cores, therefore it would detract interest.
ijor wrote:I don't think it will make porting cores less simple. Why you think it will?
olin wrote:I was under impression that PLL shift and other related changes would require modification of sys/pll.qip and pll.v. If not then great, if yes then I don't have enough knowledge about Quartus to judge how easy/hard is to make such changes dependent upon selected 'Revision', and whether the changes would be possibly accepted upstream in cores.
Sorgelig wrote:Shift the phase is the easiest thing to do. But first, you need to finish the HW design. At least you need to fix the pin assignment.
Shift amount should be done on max supposed to be supported frequency. For example on 167MHz. Lower frequencies will use the same phase shift. Just shift it a little and see how many errors you have. With iterations you will find the right amount of shift.
ijor wrote:Not sure that is the best method to find the optimal shift. The right way is through timing analysis. If you want, you can combine some measurements with timing analysis.
Sorgelig wrote:Yeah. Go measure it. Just let me find the best sit to watch
olin wrote:1) I really suck at soldering , this could indeed be true.
Sorgelig wrote:i've tried 4 layers design and found no differences from 2 layers.
olin wrote:So I generated different version of memtest between 80MHz - 150MHz in 10MHz steps, using the phase shift value of -4350ps as set in the latest memtest code. The SDRAM board run OK even on 150MHz (so far did only short term test ~5 minutes, 0 errors)
alfishe wrote:Out of curiosity - could you please describe (or point me to some tutorial) how to calculate PLL phase shifts and so one. Tried to go through altera tutorials on TimeQuest - didn't find any practical benefit yet.
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