Sorgelig wrote:DE10-nano is smaller than DE10-standard where many hot chips are close together. For example DDR memory also produce noticeable heat which just warm up the FPGA more. Also surrounded tall Arduino connectors make airflow worse and also add more heat.
May be that's why Terasic uses industrial grade FPGA.
As i've mentioned earlier, heatsink with at least slow rotating FAN is a must have addon for MiSTer.
Some cores like ao486 impossible to tweak to make it work reliably with any temperature of FPGA. Core is too big and even without much constrains took more than hour to compile.
bernouilli wrote:I think that the first thing to do is trying to run the mpu at a lower frequency. I don't think it's necessary to run at 800mhz. 400 or even 200mhz should be enough.
Then there are other paths to follow like the WFE or/and WFI states.
Sorgelig wrote:DDR is used for video scaler and it's quite busy in all cores.
ijor wrote:Btw, Terasic documentation mentions that there are three different versions of the nano. Well, actually four, A, B, B2 and C. Revision C is mentioned to use different power components. I wonder if it might have some impact on the heating. Somebody happen to have a revision C board? I bought the nano from a major Terasic distributor just a couple of weeks ago, but oddly enough is revision B, not even revision B2.
Sorgelig wrote:It's about the components on nano board - it has no relation to ARM Power Management inside FPGA chip.
ijor wrote:But since there are some claims that the heating might be related to the power logic, I am wondering if the newer revision might be better in this regard.
Sorgelig wrote:ARM CPU in Cyclone V has no power management. It cannot sleep/idle. So, it's absolutely doesn't matter if MiSTer binary takes 100% or 0% of CPU time - it won't affect the heating.
Sorgelig wrote:it's related to power logic, yes. Power logic INSIDE FPGA...
alexh wrote:Are you sure?
The design document for the Cyclone V HPS seems to say otherwise :
https://www.altera.com/en_US/pdfs/liter ... /an734.pdf
Sorgelig wrote:speak for your self I'm sure.
Instead pointing me to documents, i suggest to build your own version of Linux where you will greatly reduce the heating. Everything is open source, so just take it and improve if you think you know it better.
ijor wrote:Not too long ago you refused to accept that there was a heating problem on the DE-10 Nano at all. You were sure that it was generic to the SOC and that any board using the same FPGA should produce the same heating.
ijor wrote:Man, please stop being so aggressive. You complain all the time that it is too much work for a single developer. And you are absolutely right about that. You made an awesome job and mostly alone. But you are not helping yourself like that. Being arrogant and aggressive almost at the point of making a fight for any voice of disagreement is, IMHO, not the best way.
Newsdee wrote:However I also feel Ijor is just trying to help understand the issue, and I didn't get the vibe he was making any requests or demands.
ijor wrote:Cores should not fail if they meet timing with the slow model. It makes you think that perhaps some cores are not properly constrained.
Newsdee wrote:I have zero clue in what goes in a constraints file, but I understand it as "cores can be optimized further".
Sorgelig wrote:alexh wrote:https://www.altera.com/en_US/pdfs/literature/an/an734.pdf
Where it says otherwise?
Sorgelig wrote:Where it tells about cpu idling or dynamic frequency change like cpu in phone for example?
Sorgelig wrote:There is NO power management in its classic form. Document only describes how to reduce power by switching off unneeded components. It's applicable only for bare-metal programming, not for Linux.
Sorgelig wrote:Instead pointing me to documents, i suggest to build your own version of Linux where you will greatly reduce the heating. Everything is open source, so just take it and improve if you think you know it better.
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