Sorgelig wrote:I don't see ANY offer of help. Only complains, complains, complains.
Calm down Sorgelig. Nobody was complaining here. Certainly I wasn't. Not at all. Well, my only complain was about your aggressive attitude.
I just though (and I still think) that it is interesting to comment and exchange ideas about the heating issue. I made some actual temperature measurements comparing with other boards with the same FPGA. And I thought it would be interesting to share my measurements. I thought it is interesting to mention that the board uses an industrial grade part. And I though it was interesting to comment about the different board revisions. I never said, that the heating issue is your fault, and honestly I don't think so.
Bernouilli was saying he was looking at modifying the preloader to use a lower MPU frequency. There was no complain there and I do think it is interesting. It remains to be seen if it is worth. But I think it is an interesting experiment nevertheless.
ijor wrote:Cores should not fail if they meet timing with the slow model. It makes you think that perhaps some cores are not properly constrained.
isn't it a request?
Of course it wasn't. When we followed up I said:
Most, if not all, the other cores probably fit comfortably and they could be constrained properly (assuming they are not already). And I am not complaining to you, that should be implemented by the original developers that are very familiar with the design.
I think I couldn't make it more clear that I wasn't complaining to you nor doing any requests to you. It even wasn't my intention to complain to the original developers either. It was more of a comment that most of the cores in the "clone scene" are not properly constrained.