Core porting questions

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Sorgelig
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Re: Core porting questions

Postby Sorgelig » Wed Oct 18, 2017 8:37 am

udo wrote:Oh thanks I missed the hints in the Porting guide. So they are "only" needed for the hdmi scaler? VGA Output should work without them too?
So far I can not try it on target, because my IO-Board is still not here ...

These signals are used for VGA too. For blanking and OSD. See the sys.top.v source - it's not so big to explore.

Even though you want only ST core, i suggest to learn on more simple cores. Since many cores are ported from MiST, you can compare both versions of same core. Again - simpler core is better for start.

olin
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Re: Core porting questions

Postby olin » Tue Feb 06, 2018 8:21 pm

Another technical question:

While compiling QL core and Apple II core for DE0ns the fitter stops and complains that the device does not have enough memory M10K blocks:

Code: Select all

Error (170048): Selected device has 270 RAM location(s) of type M10K block.  However, the current design needs more than 270 to successfully fit


I found out the memory blocks are probably defined in "altsyncram" altera IP (or megafunction?), but I can not find how to view these IP blocks or modify them in Quartus 17.1 (I can only see the .v generated source). They don't appear in IP component list (only pll and pll_hdmi are listed there). If it is trivial to find and edit parameters of these memory blocks, could you point me where I can do it in Quartus? Or if there is anything else I could do (apart form rewriting the whole core, or porting it so use SDRAM) please let me know (like remove specific built-in catridge or extra add-on roms etc.).

EDIT: the X68000 core has a similar issue:

Code: Select all

Info (170034): Selected device has 270 memory locations of type M10K block. The current design requires 277 memory locations of type M10K block to successfully fit.
Info (170043): The Fitter setting for Equivalent RAM and MLAB Paused Read Capabilities is currently set to Care. More RAMs may be placed in MLAB locations if a different paused read behavior is allowed.
   Logic utilization (in ALMs)   12,370 / 15,880 ( 78 % )
   Total block memory bits   1,715,936 / 2,764,800 ( 62 % )

How to change a memory design to use MLAB location rather than M10K block for some of the memory blocks?

ijor
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Re: Core porting questions

Postby ijor » Wed Feb 07, 2018 1:13 am

olin wrote:I found out the memory blocks are probably defined in "altsyncram" altera IP (or megafunction?), but I can not find how to view these IP blocks or modify them in Quartus 17.1 (I can only see the .v generated source). They don't appear in IP component list (only pll and pll_hdmi are listed there). If it is trivial to find and edit parameters of these memory blocks, could you point me where I can do it in Quartus?


Memory block can be explicitly instantiated, such as when using megafunctions, but can also be inferred from the HDL source code. In the latter case you won't see any parameters, and won't appear in any IP component.

Or if there is anything else I could do (apart form rewriting the whole core, or porting it so use SDRAM) please let me know (like remove specific built-in catridge or extra add-on roms etc.).


There is no trivial method without being familiar with the core. The only possibility without modifying the code is to disable RAM blocks usage, so that they won't be inferred, at least for some of the cases. It is possible to use logic blocks as RAM, but it is slow and it might take too much space.

Info (170043): The Fitter setting for Equivalent RAM and MLAB Paused Read Capabilities is currently set to Care. More RAMs may be placed in MLAB locations if a different paused read behavior is allowed ...
How to change a memory design to use MLAB location rather than M10K block for some of the memory blocks?


See this: http://quartushelp.altera.com/15.0/merg ... lities.htm

Sorgelig
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Re: Core porting questions

Postby Sorgelig » Wed Feb 07, 2018 7:32 am

if at least synthesizer part finished before this error, then it's better to view compilation report. Look into "Resource utilization by Entity" and there you will have idea which module allocates M10K.

olin
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Re: Core porting questions

Postby olin » Thu Feb 08, 2018 11:57 pm

Thanks for the tips. I've managed to find the RAM definition in apple ii core and decrease it from 256kb to 128kb. The core now builds and I can run some games on it as well. I understand that some software that requires more than 128kb will not run, but still better than not having the core at all.

The X68000 will be probably tougher to resolve as it has plenty of small memory areas like 1x256 bits - I think that's the reason why the design doesn't fit. The small memory area probably occupies the whole M10kbit ram block and wastes 90% of it. I guess if I could somehow join 8 to 32 of these areas to occupy the same M10k block I could save enough ram blocks, but that would need some code changes how the data bits are retrieved (8x256) or addressed (1x 2048) from the memory block. My very naive idea would be to fit an intermediate module between the ram block (altsyncram) and the part that access it, which would do the address or bit position translation (Edit: oh wait, that means only one access to the M10k block at a time, instead of parallel access to all of them at the same time., hmm...this might not work). I'm sure there is other solutions...

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Re: Core porting questions

Postby ijor » Fri Feb 09, 2018 2:20 am

olin wrote:The X68000 will be probably tougher to resolve as it has plenty of small memory areas like 1x256 bits - I think that's the reason why the design doesn't fit. The small memory area probably occupies the whole M10kbit ram block and wastes 90% of it. I guess if I could somehow join 8 to 32 of these areas to occupy the same M10k block I could save enough ram blocks ...


You can merge two single port blocks into one dual port. Because they are dual port, they still can be accessed both of them independently at the same cycle ...

I could swear that the fitter could do some of that automatically, or at least some versions of Quartus. But right now I can't find any setting to control merging of RAM blocks.

Also note that small blocks are good candidates to be replaced with standard logic. You do can change some compiler settings for this purpose.

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Re: Core porting questions

Postby Sorgelig » Fri Feb 09, 2018 6:50 am

X68000 is far from usable state - most of games don't work or have a lot of glitches. So, you can simply skip this core - you won't loose anything.


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