olin wrote:I found out the memory blocks are probably defined in "altsyncram" altera IP (or megafunction?), but I can not find how to view these IP blocks or modify them in Quartus 17.1 (I can only see the .v generated source). They don't appear in IP component list (only pll and pll_hdmi are listed there). If it is trivial to find and edit parameters of these memory blocks, could you point me where I can do it in Quartus?
Memory block can be explicitly instantiated, such as when using megafunctions, but can also be inferred from the HDL source code. In the latter case you won't see any parameters, and won't appear in any IP component.
Or if there is anything else I could do (apart form rewriting the whole core, or porting it so use SDRAM) please let me know (like remove specific built-in catridge or extra add-on roms etc.).
There is no trivial method without being familiar with the core. The only possibility without modifying the code is to disable RAM blocks usage, so that they won't be inferred, at least for some of the cases. It is possible to use logic blocks as RAM, but it is slow and it might take too much space.
Info (170043): The Fitter setting for Equivalent RAM and MLAB Paused Read Capabilities is currently set to Care. More RAMs may be placed in MLAB locations if a different paused read behavior is allowed ...
How to change a memory design to use MLAB location rather than M10K block for some of the memory blocks?
See this: http://quartushelp.altera.com/15.0/merg ... lities.htm