JimDrew wrote:Did you add a 4.7K pull-down to the CKE line in that design? ...
To prevent overshoot, and increase the speed of the line going low
ijor wrote:Note that overshoot can be managed, at some extent, from the FPGA side. The FPGA drivers have programmable drive strength. But this is part of the compilation.
alfishe wrote:I've did an experiment when the whole FPGA bank switched to 2.5V instead of 3.3V and with Alliance SDRAM chip it gave few additional MHz of frequency ...
Sorgelig wrote:Probably will be tricky to solder.
olin wrote:Sorgelig wrote:Probably will be tricky to solder.
Then maybe try something like this:
Illustrative image how to mount vertical SDRAM board on the dual row header pins.
The board of 1.6mm thickness fits nicely in between the dual row header pins, which can be soldered to pads on the SDRAM board. You still achieve 'non-bending' connection to some of the traces (one side will have to use vias to reach the chip though) and compact size.
Sorgelig wrote:I was thinking about this connection at earlier development stages and found it less useful as current one.
i have here a SDRAM Board that is not working with any core, but running for hours through memtest 150 Mhz and also lower without any Errors. 167 Mhz give errors from start.
I think my Board is Thrash, but is memtest working correct?