Even though the latency will be "bursty", I'd like to explore the DDR3 bridging to HPS. Is there an example of how this is done? I can see the signals in the "emu" verilog module, so all the good stuff seems to be in place already - but I haven't found examples of its use on GitHub. Does this map straight to all the HPS's 1 GB memory? Do I need to reserve a range on the Linux side to be allowed to use it on the FPGA side? Is it 64-bit wide, even though the DE10-NANO h/w has 32-bit wide memory?
I'm still reading up quite a bit on all this... (and with apologies if this is the wrong thread to post in)