MiSTer: MiST on Terasic DE10-nano board.

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Sorgelig
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Re: MiSTer: MiST on Terasic DE10-nano board.

Postby Sorgelig » Wed Oct 11, 2017 9:53 pm

If joystick is not defined for specific core, then definition from Menu core will be used.

TorsteinP
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Re: MiSTer: MiST on Terasic DE10-nano board.

Postby TorsteinP » Sun Oct 15, 2017 8:54 am

My setup using Zero4U USB hub. Got PCB for I/O board 5.2. Just waiting for components from DigiKey. Also found a micro USB to mini USB cable adapter on eBay I'm waiting for.
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jcw
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Re: MiSTer: MiST on Terasic DE10-nano board.

Postby jcw » Mon Oct 16, 2017 8:23 pm

Even though the latency will be "bursty", I'd like to explore the DDR3 bridging to HPS. Is there an example of how this is done? I can see the signals in the "emu" verilog module, so all the good stuff seems to be in place already - but I haven't found examples of its use on GitHub. Does this map straight to all the HPS's 1 GB memory? Do I need to reserve a range on the Linux side to be allowed to use it on the FPGA side? Is it 64-bit wide, even though the DE10-NANO h/w has 32-bit wide memory?

I'm still reading up quite a bit on all this... (and with apologies if this is the wrong thread to post in)

Sorgelig
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Re: MiSTer: MiST on Terasic DE10-nano board.

Postby Sorgelig » Tue Oct 17, 2017 12:11 am

Check the FPGAGen core. It uses simple DDR3 access. More complex usage of DDR3 you can see in ao486 core.

DDR3 data is transferred on both edges of clock, so with 32bit bus it provides 64bit data on every clock cycle. Actually, bit-ness on MPFE bus has no relation to physical bit-ness of memory. Memory works on 800MHz while SDRAM bridge (MPFE) runs at around 100MHz, thus it may provide up to 256bit without slowing down the memory access.

jcw
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Re: MiSTer: MiST on Terasic DE10-nano board.

Postby jcw » Tue Oct 17, 2017 1:34 am

Thanks!


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