ManuFerHi wrote:For example, I changed the clk_sdram pin in SiDi for another. Now the SNES core doesn't work for me at any phase. The only way to make it work has been in phase 0 and with the option in PLL Zero delay mode. Now it is very stable.
I'm not sure using Zero delay is a good idea in this case. Zero Delay is probably not what you think. You are applying a shift blindly and without knowing. Furthermore, you are adding an unnecessary clock latency and jitter.
slingshot wrote:... The only way to make it work has been in phase 0 and with the option in PLL Zero delay mode. Now it is very stable.
Just check if the pin used is a dedicated output of a PLL. Using the dedicated output greatly reduces clock delay. However if the SDRAM doesn't require any phase shift @126 MHz, then it's really fast and connected with 0 clock skew.
No. Enabling Zero Delay Buffer mode does produce a shift. As a matter of fact you always have some kind of shift, implicitly or explicitly.
All those compensation modes compensate between the input to the PLL and one of the outputs of the PLL (something that you don't care here at all unless you cascade PLLs). They don't compensate between different PLL outputs.