Mister SNES port to MIST possible?

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vebxenon
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Re: Mister SNES port to MIST possible?

Postby vebxenon » Thu Sep 26, 2019 1:51 pm

squid4 wrote:I've added documentation to the MIST WIKI https://github.com/mist-devel/mist-board/wiki/CoreDocSNES


Great :cheers:
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Re: Mister SNES port to MIST possible?

Postby sebdel » Thu Sep 26, 2019 2:07 pm

squid4 wrote:I've added documentation to the MIST WIKI https://github.com/mist-devel/mist-board/wiki/CoreDocSNES

Thanks, very helpful. No big deal but you recommend SAV files of 64K but then create 32K ones with the dd command.

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Re: Mister SNES port to MIST possible?

Postby squid4 » Thu Sep 26, 2019 6:54 pm

I've added a simple script for the NSRT tool to prepare ROMS & SAV files for this core. It's on the Wiki above.

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Re: Mister SNES port to MIST possible?

Postby slingshot » Fri Sep 27, 2019 11:43 am

Please try:
https://github.com/gyurco/SNES_MiSTer/r ... /tag/test7

If it's still stable, then I'll put it to mist-binaries.

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Re: Mister SNES port to MIST possible?

Postby vebxenon » Fri Sep 27, 2019 12:20 pm

slingshot wrote:Please try:
https://github.com/gyurco/SNES_MiSTer/r ... /tag/test7

If it's still stable, then I'll put it to mist-binaries.


Thanks! :cheers: I'm going to test it :D
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Re: Mister SNES port to MIST possible?

Postby vebxenon » Fri Sep 27, 2019 12:39 pm

Test 7 works perfect!! :cheers: :cheers:
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Re: Mister SNES port to MIST possible?

Postby vebxenon » Fri Sep 27, 2019 1:43 pm

Well, after several minutes, Aero Fighers (USA) hangs :shrug: in demo mode.
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Re: Mister SNES port to MIST possible?

Postby squid4 » Fri Sep 27, 2019 5:24 pm

Haven't noticed much difference yet but Chrono Trigger opening title screen seems to have a graphic corruption (small flickering block lower right) more frequent than test6. It's the only game I've seen since test6 with any graphics corruption. Usually a soft reset clears the corruption.

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Re: Mister SNES port to MIST possible?

Postby DistWave » Sat Sep 28, 2019 8:14 am

I confirm that Test7 and Test8 are a step back in stability in my Mist

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Re: Mister SNES port to MIST possible?

Postby slingshot » Sat Sep 28, 2019 10:31 am

Chrono Trigger attract mode is running for 20 minutes without any glitch with this:

https://github.com/gyurco/SNES_MiSTer/r ... /tag/test9

I should stop updating this core.

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Re: Mister SNES port to MIST possible?

Postby squid4 » Sat Sep 28, 2019 11:47 am

V9 looking good!

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Re: Mister SNES port to MIST possible?

Postby rampa » Sun Sep 29, 2019 10:51 am

slingshot wrote:Chrono Trigger attract mode is running for 20 minutes without any glitch with this:

https://github.com/gyurco/SNES_MiSTer/r ... /tag/test9

I should stop updating this core.


On the mistica sdram, the image goes to black ater random time (sound still playing) the latest stable rbf on mistica is test3.

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Re: Mister SNES port to MIST possible?

Postby gibs » Sun Sep 29, 2019 2:19 pm

@slingshot

Unfortunately for me this is the only core that doesn't work with my LCD screen.

The screen flicker and turn to black, and come back then turn to black...

if you can fix that before stopping updating.... :angel:

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Re: Mister SNES port to MIST possible?

Postby slingshot » Sun Sep 29, 2019 2:44 pm

gibs wrote:@slingshot

Unfortunately for me this is the only core that doesn't work with my LCD screen.

The screen flicker and turn to black, and come back then turn to black...

if you can fix that before stopping updating.... :angel:

In both PAL and NTSC?

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Re: Mister SNES port to MIST possible?

Postby desUBIKado » Sun Sep 29, 2019 8:03 pm

rampa wrote:
slingshot wrote:Chrono Trigger attract mode is running for 20 minutes without any glitch with this:

https://github.com/gyurco/SNES_MiSTer/r ... /tag/test9

I should stop updating this core.


On the mistica sdram, the image goes to black ater random time (sound still playing) the latest stable rbf on mistica is test3.


It's a problem of memory chip. Older Misticas have MICRON memories, and these ones work fine with all test SNES cores (my Mistica has MICRON memory), but newer Misticas have Alliance memories, and I think with these memory only till TEST3 core worked fine.

MICRON memories have two notches, one at the top and one at the bottom. The Alliance ones haven't notches.

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Re: Mister SNES port to MIST possible?

Postby gibs » Mon Sep 30, 2019 4:29 am

slingshot wrote:
gibs wrote:@slingshot

Unfortunately for me this is the only core that doesn't work with my LCD screen.

The screen flicker and turn to black, and come back then turn to black...

if you can fix that before stopping updating.... :angel:

In both PAL and NTSC?


Even the menu is not stable, I can't barely select a ROM.

I have switched to PAL and now the picture is stable during the menu and games.

do you want a video of the issue ?

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Re: Mister SNES port to MIST possible?

Postby Televicious » Mon Sep 30, 2019 7:50 am

slingshot wrote:Chrono Trigger attract mode is running for 20 minutes without any glitch with this:

https://github.com/gyurco/SNES_MiSTer/r ... /tag/test9

I should stop updating this core.


It is already more stable and robust than the NES core.

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Re: Mister SNES port to MIST possible?

Postby slingshot » Mon Sep 30, 2019 9:06 am

desUBIKado wrote: have Alliance memories, and I think with these memory only till TEST3 core worked fine.

What's the exact part number?
Btw, my MiST has Hynix SDRAM, the Microns are discontinued.

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Re: Mister SNES port to MIST possible?

Postby slingshot » Mon Sep 30, 2019 9:14 am

gibs wrote:I have switched to PAL and now the picture is stable during the menu and games.


If it works in PAL mode, then use that.

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Re: Mister SNES port to MIST possible?

Postby gibs » Mon Sep 30, 2019 3:52 pm

slingshot wrote:
gibs wrote:I have switched to PAL and now the picture is stable during the menu and games.


If it works in PAL mode, then use that.


Ok, and is there a way to memorise this setting ? :)
Because it's painfull at launch to select PAL. :)

I tried the save settings after setting it to PAL, but doesn't save...

Thanks

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Re: Mister SNES port to MIST possible?

Postby ManuFerHi » Mon Sep 30, 2019 3:56 pm

slingshot wrote:
desUBIKado wrote: have Alliance memories, and I think with these memory only till TEST3 core worked fine.

What's the exact part number?
Btw, my MiST has Hynix SDRAM, the Microns are discontinued.


Until 2018 the same as the original mist MT48LC16M16A2P-75, but these memories became obsolete and difficult to acquire.
As of 2019, Alliance memory AS4C16M16SA-6TCN (the same as Mister).
The SNES cores with these memories work perfectly until the TEST3 version, as of TEST4 they are unstable and shortly after loading the game starts the failures.

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Re: Mister SNES port to MIST possible?

Postby slingshot » Mon Sep 30, 2019 4:08 pm

-6 is even higher speed grade, shouldn't be a problem from ACTIVE-to-ACTIVE timing. Maybe contention on the data bus can be the problem (e.g. one high-Z cycle should be between a read and write phase, however this is not true, since then the sdram controller would be too slow). It would be worth to experiment with the phase shift of the sdram clock.

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Re: Mister SNES port to MIST possible?

Postby alexh » Mon Sep 30, 2019 6:35 pm

Does SDR SDRAM have a concept of additive latency? It's a little used feature of DDR SDRAM which I use at work to increase bus utilisation.

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Re: Mister SNES port to MIST possible?

Postby ManuFerHi » Mon Sep 30, 2019 7:01 pm

I don't think it's the frequency, I've tried to raise from 128.92 to 133mhz step by step and it's always the same result. In addition the cores before to TEST4B work perfectly and go at the same speed and phase, but there was an important change between these two versions in memory management.

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Re: Mister SNES port to MIST possible?

Postby slingshot » Mon Sep 30, 2019 7:03 pm

alexh wrote:Does SDR SDRAM have a concept of additive latency? It's a little used feature of DDR SDRAM which I use at work to increase bus utilisation.

I had to search what is that - so no :)
Btw, the problem is: issue 3 full commands (ACTIVE, READ/WRITE, and get the data) to 3 separate banks in 8 cycles without any clash, and obey every timing restrictions at @128 MHz. And I think all obeyed, but not sure about that extra cycle is needed between a read and write. Seems on my device, it's OK without that. But to be sure, the SDRAM data bus should be measured with an oscilloscope. Or just experiment with the clock phase, and maybe the input delays in the .sdc file.


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