NEW OR UPDATED ARCADE CORES

[DrOG]

I do not have time for a test, I have to work.

Edit: need Feedback about Controls(are rotated Controls needed) and RGB Output

Hi!

Fine over SCART (see attachment), and DB-9 control works properly also. But some menu items don't seem to work as they should, and I'm unable to insert coin with Esc as well...

[Gehstock]

-Repair Controls for Normal Screen Direction(was Switched)
-Change Dip Setting(No rotated Screen for Player 2)
-Remove not working Menu Items

should fully working but needs still to much Le´s

[DanyPPC]

Thanks, Time Pilot works very well

[hyperterminal]

Thank you Gehstock for this new arcade core.

The hardware for the game Pooyan is very similar to Time Pilot. Would it be possible to make a core for Pooyan as well?

[vebxenon]

It works like a charm!!

Thanks very very much! I've also tested last Galaga update, and it runs perfectly.

Thanks very much, Gehstock!

[Gehstock]

Other Rom Structure, maybe Dar will help with correct mapping

http://www.solvalou.com/subpage/arcade_roms/T/timepltc

http://www.solvalou.com/subpage/arcade_roms/P/pooyan

[Gehstock]

Computer Space, thanks to Sorgelig

Start: ESC
Controls: Arrow Keys/Space or Joy


EDIT: RGB should work now

[Gehstock]

Galaga Update, thanks to Dar

[DanyPPC]

WoW !

You are great !

ComputerSpace: "No Signal" on my Samsung TV/Monitor via VGA

[Darfpga]

Pooyan FPGA arcade game. Source available at :

https://sourceforge.net/projects/darfpga/files/Software%20VHDL/pooyan

Early release, feel free to port to MiST/MiSTer.

[Gehstock]

Awesome Thank you

[DrOG]

Computer Space, thanks to Sorgelig

Start: ESC
Controls: Arrow Keys/Space or Joy

EDIT: RGB should work now

It does not work on my Samsung LE40B650 over SCART...

[ericgus]

Awesome Thank you

Is this core binary available somewhere?

[Gehstock]

is WIP actual we have no Sound, lack of BRAM, will upload Code hopefully will someone find some Bytes .
is the same LE Leak like the Time Pilot Core. Without RGB and OSD can try to add sound.

[DanyPPC]

Thanks

[Darfpga]

Pooyan new release. No big update, mainly readme.

https://sourceforge.net/projects/darfpga/files/Software%20VHDL/pooyan/

[Gehstock]

Thank You very much

[Darfpga]

is WIP actual we have no Sound, lack of BRAM, will upload Code hopefully will someone find some Bytes .
is the same LE Leak like the Time Pilot Core. Without RGB and OSD can try to add sound.

No sound : bizarre, sound is done!
Lack ok BRAM : bizarre, around 30% on Max10-50!
LE Leak : what do you mean ?

Very often vhld PROM files doesn't fill entire address length. Eg: time_pilot_prog.vhd only fill 24Ko although address range covers 32Ko. With my compiler (quartus 16.1) this is not a problem, there is only a warning saying that the last 8Ko will be filled with zeros. Then assember/fitter remove all those zeros and no memory is required to store them. This can be seen by looking the fit report file.

The only counter part is that simulator (altera-sim) won't accept to load and terminate with an error. If you need to run simulator you have to manualy add zeros between 24Ko and 32Ko. Then everything is ok.

In the same way, 4bits width prom contains 8bits data in vhdl files, compiler removes the 4 always null bits and don't use additional ram ressource.

[Gehstock]

I do not have the experience but with the MIST function, Time Pilot just fits, but Pooyan is a bit bigger

Code: Select all

Flow Status   In progress - Thu Nov 09 22:29:20 2017
Quartus II 64-Bit Version   13.1.0 Build 162 10/23/2013 SJ Web Edition
Revision Name   time_pilot_mist
Top-level Entity Name   time_pilot_mist
Family   Cyclone III
Device   EP3C25E144C8
Timing Models   Final
Total logic elements   20,410
Total combinational functions   13,212
Dedicated logic registers   8,349
Total registers   8349
Total pins   29
Total virtual pins   0
Total memory bits   517,888
Embedded Multiplier 9-bit elements   2
Total PLLs   1

Code: Select all

Flow Status   Flow Failed - Thu Nov 09 22:28:54 2017
Quartus II 64-Bit Version   13.1.0 Build 162 10/23/2013 SJ Web Edition
Revision Name   pooyan_mist
Top-level Entity Name   pooyan_mist
Family   Cyclone III
Device   EP3C25E144C8
Timing Models   Final
Total logic elements   20,457 / 24,624 ( 83 % )
Total combinational functions   13,272 / 24,624 ( 54 % )
Dedicated logic registers   8,350 / 24,624 ( 34 % )
Total registers   8350
Total pins   29 / 83 ( 35 % )
Total virtual pins   0
Total memory bits   550,656 / 608,256 ( 91 % )
Embedded Multiplier 9-bit elements   2 / 132 ( 2 % )
Total PLLs   1 / 4 ( 25 % )

Error (170040): Can't place all RAM cells in design
Info (170034): Selected device has 66 memory locations of type M9K. The current design requires 69 memory locations of type M9K to successfully fit.
Info (170033): Memory usage required for the design in the current device: 105% M9K memory block locations required
Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:01
Info (11888): Total time spent on timing analysis during the Fitter is 0.51 seconds.
Error (171000): Can't fit design in device

dont forget the Ram Cells for the Scandoubler

[Gehstock]

is a new scramble or pengo core needed? i can try to port the new Mister Cores .

[Sorgelig]

Not every bit of BRAM can be used. They are used by blocks (hence BRAM name). So it depends on width and dept of required RAM and how it divided to these blocks. You cannot control it actually..

[ijor]

Sometimes it is possible to pool and combine multiple logical blocks in a single physical one. Since FPGA RAM is dual port, each logical block can be accessed independently, even with a different clock. Quartus can sometimes do this automatically. I don't remember if there is an option that must be enabled that is disabled by default.

Sometimes a RAM block can be replaced with LEs. But all of this kind of tweaking is much more difficult when you are not very familiar with the design.

dont forget the Ram Cells for the Scandoubler

Scan doubling doesn't have low latency requirements. It might be possible to use external DRAM. But this again, depends on the DRAM usage by the rest of the design.

[DrOG]

is WIP actual we have no Sound, lack of BRAM, will upload Code hopefully will someone find some Bytes .
is the same LE Leak like the Time Pilot Core. Without RGB and OSD can try to add sound.

Actually this version is already well usable: perfect over SCART and with DB-9 joy!

Sound is missing, but I can live without that!

Thanks for porting this awesome arcade core, Gehstock!

I have a question: I know your River Raid core is still in beta stage, but would it be possible to add DB-9 joy support to the last version hich was compatible with my tv (had some color issues, i.e. the water was red, but this doesn't bother me). That's the only reason (missing retro joystick support) I don't use it more often...

Thanks in advance: Gábor

[ericgus]

is WIP actual we have no Sound, lack of BRAM, will upload Code hopefully will someone find some Bytes .
is the same LE Leak like the Time Pilot Core. Without RGB and OSD can try to add sound.

Ah ok .. I thought it was another completed one.. no worries..

Thanks for posting what you do have ..!! looks great so far!

[Gehstock]

WoW !

You are great !

ComputerSpace: "No Signal" on my Samsung TV/Monitor via VGA

Computer Space, thanks to Sorgelig

Start: ESC
Controls: Arrow Keys/Space or Joy

EDIT: RGB should work now

It does not work on my Samsung LE40B650 over SCART...

I have Signal via Scart and VGA