NEW OR UPDATED ARCADE CORES

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squid4
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Re: NEW OR UPDATED ARCADE CORES

Postby squid4 » Tue Nov 26, 2019 8:00 pm

Are any of Gehstock's tron, dominoman etc working on 15khz? Just get a blank screen, tiger road just a purple screen for me. 22/11 builds.

Update: Just realised the source is updated but rbf not compile, still WIP.

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Re: NEW OR UPDATED ARCADE CORES

Postby Darfpga » Fri Nov 29, 2019 8:55 pm

Zaxxon VHDL source code for de10_lite available at :

https://sourceforge.net/projects/darfpg ... re%20VHDL/

TV 15kHz mode only, No sound atm.

Feel free to port to MiST/MiSTer.

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Re: NEW OR UPDATED ARCADE CORES

Postby vebxenon » Sat Nov 30, 2019 9:09 am

vebxenon wrote:I've updated Dig Dug from Gehstock. Now at bottom and left side glitched graphics appear :shrug: . Can this problem be fixed?

https://github.com/Gehstock/Mist_FPGA/b ... ST/Release


I'm the only with this problem? :shrug:
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Re: NEW OR UPDATED ARCADE CORES

Postby vebxenon » Sat Nov 30, 2019 9:09 am

Darfpga wrote:Zaxxon VHDL source code for de10_lite available at :

https://sourceforge.net/projects/darfpg ... re%20VHDL/

TV 15kHz mode only, No sound atm.

Feel free to port to MiST/MiSTer.


Great! :cheers:
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Re: NEW OR UPDATED ARCADE CORES

Postby vebxenon » Sat Nov 30, 2019 9:12 am

Just a computer and videogame lover :)

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Re: NEW OR UPDATED ARCADE CORES

Postby DrOG » Sun Dec 01, 2019 5:14 am

Thanks to Jotego for the core and to vebxenon for pointing to it! :cheers: :cheers:

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Re: NEW OR UPDATED ARCADE CORES

Postby Darfpga » Sun Dec 01, 2019 9:19 pm

slingshot wrote:
Darfpga wrote:
I'am going to give it a try in a while. Should be easier in 15kHz mode since pixels lasts twice.

Thanks! Actually the current rate would be good, if the core would use the data when all the 4 bytes arrived addressed by the mux, not immediately after each byte.

I've delayed the data feeding to line buffer and added sdram 8 words read burst. Works not so bad but still got what seems to be a memory refresh problem.

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Re: NEW OR UPDATED ARCADE CORES

Postby slingshot » Mon Dec 02, 2019 11:14 am

Darfpga wrote:
slingshot wrote:
Darfpga wrote:
I'am going to give it a try in a while. Should be easier in 15kHz mode since pixels lasts twice.

Thanks! Actually the current rate would be good, if the core would use the data when all the 4 bytes arrived addressed by the mux, not immediately after each byte.

I've delayed the data feeding to line buffer and added sdram 8 words read burst. Works not so bad but still got what seems to be a memory refresh problem.

8 words burst? That's also an insane amount of bandwidth :)
I almost could do it with 32 bit burst - the address setup could be done earlier for the 2nd, 3rd and 4th word (basically 8 cycles earlier), but not for the first one - the sprite code number fetch is just one cycle before the first data is needed. I see on the original schematics that the sprite code (upper bits of the ROM address) is fetched into a 8-bit D-Flip-flop. I wonder when it's done. I'm sure it's not just 1 40MHz clock cycle before the sprite data needed.

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Re: NEW OR UPDATED ARCADE CORES

Postby Darfpga » Mon Dec 02, 2019 11:11 pm

I just deliver an update for discs of tron with external (sd)ram access.

https://sourceforge.net/projects/darfpg ... leted=true

slingshot wrote:8 words burst? That's also an insane amount of bandwidth :)
I almost could do it with 32 bit burst - the address setup could be done earlier for the 2nd, 3rd and 4th word (basically 8 cycles earlier), but not for the first one - the sprite code number fetch is just one cycle before the first data is needed. I see on the original schematics that the sprite code (upper bits of the ROM address) is fetched into a 8-bit D-Flip-flop. I wonder when it's done. I'm sure it's not just 1 40MHz clock cycle before the sprite data needed.


I keep 8 words burst, it's ok for my board since the other roms stay inside fpga. I understand that you want to preserve bandwith for other accesss. 8 words burst is the less overall bandwidth consumption but I agree that it makes a big contention time. Anyway you can split the burst in smaller part but the global overhead will increase. It's easy to modify the sprite machine to add more cycles. I think that there is enough free time in 15kHz but keep in mind that there was already graphics sprite problems for discs of tron when the sprite machine was running at 20MHz in 31kHz.

With 8 words burst I have to replicate roms content in both direct and reverse bytes order (per 16 bytes packets) since sprite machine required both reading direction. If you split into 2 words burst you can manage that problem without replication. In any case the most significant address bit tell s for normal or reverse order needed. Look at my loader code.

Now I am going to prepare update for timber.

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Re: NEW OR UPDATED ARCADE CORES

Postby slingshot » Tue Dec 03, 2019 6:34 am

Darfpga wrote:I just deliver an update for discs of tron with external (sd)ram access.

https://sourceforge.net/projects/darfpg ... leted=true

slingshot wrote:
I keep 8 words burst, it's ok for my board since the other roms stay inside fpga. I understand that you want to preserve bandwith for other accesss. 8 words burst is the less overall bandwidth consumption but I agree that it makes a big contention time. Anyway you can split the burst in smaller part but the global overhead will increase. It's easy to modify the sprite machine to add more cycles. I think that there is enough free time in 15kHz but keep in mind that there was already graphics sprite problems for discs of tron when the sprite machine was running at 20MHz in 31kHz.


That's true, with 8 width burst, the state machine will be too long. However the problem is not with the additional reads, but with the first one. And you should do something with that even in a 8 word burst (the address should be set up even earlier), so I'm not worried :)

With 8 words burst I have to replicate roms content in both direct and reverse bytes order (per 16 bytes packets) since sprite machine required both reading direction. If you split into 2 words burst you can manage that problem without replication. In any case the most significant address bit tell s for normal or reverse order needed. Look at my loader code.

Now I am going to prepare update for timber.


Good, thank you!

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Re: NEW OR UPDATED ARCADE CORES

Postby slingshot » Thu Dec 05, 2019 9:14 am

Darfpga wrote:
Now I am going to prepare update for timber.


Timber works! It's easy if you know just have to delay sprite_on_line a bit :)

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Re: NEW OR UPDATED ARCADE CORES

Postby Gehstock » Thu Dec 05, 2019 11:29 am

:mrgreen:

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Re: NEW OR UPDATED ARCADE CORES

Postby Darfpga » Fri Dec 06, 2019 12:22 pm

Discs of tron and Timber updated for de10_lite.

Timber is now ok with sdram loader to hold graphic sprites.

https://sourceforge.net/projects/darfpg ... re%20VHDL/

Seems to be useless for MiST since I just discover that sdram adaptation was already done.

After a quick glance it seems that MiST sdram interface is more versatile than mine. Good job.

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Re: NEW OR UPDATED ARCADE CORES

Postby Gehstock » Fri Dec 06, 2019 12:47 pm

Thanks for all your Work.

Tapper and Timber Released for MiST other Cores will Follow.

Also Xevious is done by Slingshot

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Re: NEW OR UPDATED ARCADE CORES

Postby vebxenon » Fri Dec 06, 2019 2:50 pm

Gehstock wrote:Thanks for all your Work.

Tapper and Timber Released for MiST other Cores will Follow.

Also Xevious is done by Slingshot


:cheers: :cheers:
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Re: NEW OR UPDATED ARCADE CORES

Postby Gehstock » Fri Dec 06, 2019 4:13 pm

New Core Discs of Tron

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Re: NEW OR UPDATED ARCADE CORES

Postby seastalker » Sun Dec 08, 2019 3:56 pm

Tapper? Amazing! I love playing the Coleco version!

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Re: NEW OR UPDATED ARCADE CORES

Postby squid4 » Mon Dec 09, 2019 10:49 pm

Thanks for Tapper/Domino/Timber and Bomb Jack. Bomb Jack is looking perfect!

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Re: NEW OR UPDATED ARCADE CORES

Postby vebxenon » Mon Dec 09, 2019 11:59 pm

vebxenon wrote:I've updated Dig Dug from Gehstock. Now at bottom and left side glitched graphics appear :shrug: . Can this problem be fixed?

https://github.com/Gehstock/Mist_FPGA/b ... ST/Release


Still happens to me :shrug:
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Re: NEW OR UPDATED ARCADE CORES

Postby vebxenon » Tue Dec 10, 2019 12:00 am

I've seen that there is a snapshot of Atari Tetris :cheers: Hope graphical problems will be able to be fixed :D
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Re: NEW OR UPDATED ARCADE CORES

Postby wwark » Wed Dec 11, 2019 6:37 am

Hi,

I have a question related to the xevious Core I'm using it on Mister side.
I would like to know if the xevious core on Mist SIde is able to play Super Xevious (or it needs a dedicated core) In mame code Super Xevious is a clone of Xevious.
Thanks !

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Re: NEW OR UPDATED ARCADE CORES

Postby Gehstock » Wed Dec 11, 2019 7:44 am

From the ReadMe
XEVIOUS.ROM is required at the root of the SD-Card.
Menu Item for Super Xevious
SXEVIOUS.ROM for Super Xevious (buggy for the First Game then it´s ok)



Diffenences are only in a Dip Switch(Freeze)

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Re: NEW OR UPDATED ARCADE CORES

Postby slingshot » Wed Dec 11, 2019 10:14 am

vebxenon wrote:I've seen that there is a snapshot of Atari Tetris :cheers: Hope graphical problems will be able to be fixed :D

Unfortunately the cores from Mr. X are using not very FPGA-friendly clocking. Almost impossible to get a stable build from them.

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Re: NEW OR UPDATED ARCADE CORES

Postby vebxenon » Wed Dec 11, 2019 3:18 pm

slingshot wrote:
vebxenon wrote:I've seen that there is a snapshot of Atari Tetris :cheers: Hope graphical problems will be able to be fixed :D

Unfortunately the cores from Mr. X are using not very FPGA-friendly clocking. Almost impossible to get a stable build from them.


:| :(
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Re: NEW OR UPDATED ARCADE CORES

Postby wwark » Thu Dec 12, 2019 4:48 am

@Gehstock,
Sorry I don't check the readme of mist.
There is no note related to Super Xevious in the readme of Mister.
I will try to load first Xevious and Super Xevious after.
If it is not working I will open a ticket on Mister side.
Thanks again.


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