slingshot wrote:It seems the built-in IDE in RISC OS (with the 82c711 chip) works only if the FDC is also used from that chip.
Yes, I think this is correct. It is either 1772-and-6551 or 82c710/82c711-all-the-way. If you want to keep the 1772 and support a harddisc out of the box with RISC OS 3.1, you'd need to simulate the MFM/ST506 controller used inside the Archimedes 4xx range, a Hitachi HD63463. However, the possible size of an MFM harddisc was quite limited, I think 56 MB or so?
That means a brand new FDC is required.
I hoped that somewhere in FPGA universe, someone already recreated the 82c710 or something very similar (SMC665...). What does ao486 on MISTer use for I/O?
However I found the Risc Developments IDE interface, which has 16k ROM only (easily fits into the FPGA internal RAM), is this interface good enough?
Any IDE podule you could recreate would be fine, I don't think they differed much technically, most of the difference was the software. I mentioned the ICS IDE podule because it seemed quite common back in the day, and ZIDEFS by John Kortink from here http://www.zeridajh.org/software/zidefs/index.htm
is easily available and known-good (it is still used today in ICS podule recreations!). The ZIDEFS ROM is only 8 KB by the way. ZIDEFS supports up to 4 partitions, RISC OS before version 3.6 was limited to 512 MB per partition, I am not sure if the Risc Developments software supported partitioning.
Here is a podule hardware design compatible with ZIDEFS: https://stardot.org.uk/forums/viewtopic ... 16&t=15205
Usually, the ROM on a podule (or more precise: the modules it contains) would be copied by the RISC OS podule loader into the computer's RAM on startup. So you wouldn't need FPGA internal RAM, you'd just treat it as an addition to the RISC OS ROM file??? You'll notice that I have no idea about that FPGA stuff, so I don't know how straightforward any implementation would be...