Work on the Minimig core?

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Re: Work on the Minimig core?

Postby slingshot » Thu Nov 07, 2019 9:12 am

Strange, it works for me.

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Re: Work on the Minimig core?

Postby slingshot » Thu Nov 07, 2019 10:24 am

tobiflex wrote:

Code: Select all

git reset --hard 377a766
git push --force

I had it done. :cheers:

Good :)
Just don't use it too often. You can make annoying surprises for projects which are using your repo with changing histories. As I see you're using the github webinterface to upload? I think it worth to learn at least the basics of the 'git' command, you can have much more control over your repo.

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Re: Work on the Minimig core?

Postby fpgaarcade » Thu Nov 07, 2019 12:01 pm

Tobi! nice to see you.


I have attempted to pull apart the TG68K so I could understand/maintain it and potentially pipeline it.

I haven't looked at my variant for a while, but shoved it public in a slightly bust state - I seem to have broken 68000 interrupts I think.
https://github.com/FPGAArcade/replay_co ... b/cpu/m68k

I added cas2/cmp2 and a bunch of other stuff. Not in the most elegant way I admit (I've been working on a new design for a while) but it works and passes the Motorola 020 test suite (with one V flag exception)


I'm not sure if it's easier to cherry pick and back port to the TG68K or do them from scratch.
I've taken a few of the latest tweaks but not all, I'll look this afternoon and I'll attempt to get the simulator regression suite dusted off again.

/MikeJ

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Re: Work on the Minimig core?

Postby fpgaarcade » Thu Nov 07, 2019 12:03 pm

p.s the name change was just so I could keep track of it / differentiate it from the many TG68K variants.
I'll add the original license header back or make it more obvious where it came from.

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Re: Work on the Minimig core?

Postby MasterOfGizmo » Thu Nov 07, 2019 3:04 pm

Wow ... seems the crowd is finally complete.

We should probably agree on one common version to work on. Any suggestions which version to base it on?
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Re: Work on the Minimig core?

Postby ex68k » Thu Nov 07, 2019 3:42 pm

I guess, it is best to use TobiFlex's GIT, as it is, where people would look for it.

https://github.com/TobiFlex/TG68K.C

There are to many spin offs already, with different content.

And, probably make a new thread, about the tg68k only?

Cheers

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Re: Work on the Minimig core?

Postby fpgaarcade » Thu Nov 07, 2019 4:00 pm

Hiya Till.
Yeah I've been a bit swamped with work/life and am getting back up to speed.

Agreed, it's Tobiflex's design and if he's interested in supporting it again then we should have that as the master.

I'll continue to work on my test suite and I can run up both variants and compare. Will commit the wip to the public repos.

I would like to continue to work on the M68K variant as it has far less loops in the code and appears to synthesize better. I guess we wait for Tobiflex's view
/Mike

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Re: Work on the Minimig core?

Postby slingshot » Thu Nov 07, 2019 4:54 pm

Oh, everybody here...

Just noticed the comment at the end of the "old" TG68k.vhd:
- --when the instruction has completed, the decremented address
- --register contains the address of the last operand stored. For
- --the MC68020, MC68030, and MC68040, if the addressing
- --register is also moved to memory, the value written is the
- --initial register value decremented by the size of the oper-
- --ation. The MC68000 writes the initial register value
- --(not decremented).

But according to the cputester, this is not implemented for 68020 (the stored value is not the predecremented one).

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Re: Work on the Minimig core?

Postby fpgaarcade » Thu Nov 07, 2019 5:58 pm

I'm really keen for us to get all known fixes in place - and close the box on this for now.

I can check back here, but is it better to have an email group or perhaps slack?
/Mike

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Re: Work on the Minimig core?

Postby MasterOfGizmo » Thu Nov 07, 2019 8:30 pm

fpgaarcade wrote:I would like to continue to work on the M68K variant as it has far less loops in the code and appears to synthesize better.


But that's exactly what i'd like to avoid. Why would we want to have two branches of tg68k? Is there any advantage having two of them and basically copying all patches and fixes forth and back?

Maybe you want to advertise your version a little bit. I don't know if Tobias e.g. cares for the tg name much and I also don't know how much you'd like to avoid it. But imho it would be sad if the main reason for the fork is the naming scheme ...

But that's only my point of view. I can live with whatever you agree on. I would just like to see all work being focussed on one version and that version to include all known improvements. Are there any known disadvantages of your m68k version over the current tg68k? If yes, can these be easily fixed?
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Re: Work on the Minimig core?

Postby MasterOfGizmo » Thu Nov 07, 2019 8:35 pm

fpgaarcade wrote:I'm really keen for us to get all known fixes in place - and close the box on this for now.

I fully agree on this. Having a stable 68k core that passes all 68k and 020 tests is the goal.

Whereas there are a few things i'd implement as a compile time option like the barrel shifter and the hw multiplier. Maybe one day someone would like to add the 030 mmu ... who knows?

fpgaarcade wrote:I can check back here, but is it better to have an email group or perhaps slack?


Sure. But that really means that we do cooperate on one single core.
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Re: Work on the Minimig core?

Postby tobiflex » Thu Nov 07, 2019 8:49 pm

Hello everybody
In my opinion, the version of Mike is very interesting - thanks for that.
but because I would like to maintain the TG68 I would like to stay with my version on GITHUB.
Mike has used in his core records. I think I'll try that too. This is new to me and I like it.

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Re: Work on the Minimig core?

Postby fpgaarcade » Thu Nov 07, 2019 8:50 pm

Till,
I was kinda arguing the other way round - let's update TG68K. The only reason I changed the name was the modifications I was making were a bit radical and I wasn't sure TB would approve - at least I would have liked to run it past him.

Although I've pulled out the instruction decoder, I haven't managed to remove all loops from it yet, but I'm close. This would potentially allow pipeline stages to be inserted etc. I've also been working on making it 32 bit externally.

What is probably the most pragmatic option is to see if I can fit my changes into TB's current code.

If you like the restructuring changes I made in M68K, we can merge my stuff into the tg68k codebase or focus on mine, really up to TB to decide which one we use. I don't mind either away.

/Mike

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Re: Work on the Minimig core?

Postby fpgaarcade » Thu Nov 07, 2019 8:52 pm

tobiflex wrote:Hello everybody
In my opinion, the version of Mike is very interesting - thanks for that.
but because I would like to maintain the TG68 I would like to stay with my version on GITHUB.
Mike has used in his core records. I think I'll try that too. This is new to me and I like it.


We crossed posts there.
I am Very happy for you to be the maintainer and I will support you however you wish.
Additionally, if you want to include my record changes then I can continue to work on pipelining your core.

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Re: Work on the Minimig core?

Postby tobiflex » Thu Nov 07, 2019 9:16 pm

Sorry i must write this in German an hope someon can it translate.
Der TG68K hat einen grossen Mangel. Bei Speicherzugriffen wird die Adresse erst in dem Takt, in dem auch der Zugriff erfolgt durch eine Addition erzeugt. Deshalb ist die Adresse auch nicht sofort nach der Taktflanke gültig.
Die nächste Schwäche ist eine Rückwirkung des internen Prozessorzustandes in den Dekoder.
Ich habe nebenbei an einem neuen Design gearbeitet, das diese Schächen nicht hat. Die Pipeline ist für die Adressberechnung eine Stufe länger. Der Decder ist rückwirkungsfrei.
Mein Plan würde jetzt so aussehen:
1. Alle wichtigen Sachen im TG68K ergänzen und fixen.
wenn fertig ->
2. Den NTG68.W fertig zu einem 68000/10 entwickeln.
wenn fertig ->
3. Die Entwicklung des NTG68.L mit 32-Bit Speicherinterface zu starten und den auch mindestens bis zum 68020 zu bringen.

goole translater:
The TG68K has a big drawback. In the case of memory accesses, the address is generated only in the cycle in which the access also takes place by means of an addition. Therefore, the address is not valid immediately after the clock edge.
The next weakness is a feedback of the internal processor state into the decoder.
Incidentally, I've been working on a new design that does not have those holes. The pipeline is one step longer for the address calculation. The decoder is non-reactive.
My plan would now look like this:
1. Complete and fix all important things in the TG68K.
when finished ->
2. Develop the NTG68.W ready for a 68000/10.
when finished ->
3. To start the development of the NTG68.L with 32-Bit memory interface and to bring that also at least up to the 68020.
Top

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Re: Work on the Minimig core?

Postby fpgaarcade » Thu Nov 07, 2019 10:00 pm

Google translate is enough, please feel free to write in German.

I don't have a problem with the single cycle access. There are slight timing complications into the cache but manageable.

Plan sounds good.

btw We are working on a new 68060 class core based on a RISCV pipeline and microcoding. The idea is to add dedicated front end hardware which does EA decode etc and improve efficiency. Perhaps when the current core is stable we can pool resources on a next-gen core.

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Re: Work on the Minimig core?

Postby kolla » Thu Nov 07, 2019 10:39 pm

For 68000 there is also ljor’s core, perhaps unknown to @fpgaarcade and @tobiflex?

http://www.atari-forum.com/viewtopic.php?f=28&t=34730

Would it not make sense to use that for the “pure” 68000 Amiga/Atari ST experience, and focus on 020+ for tg68?
-- kolla

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Re: Work on the Minimig core?

Postby fpgaarcade » Fri Nov 08, 2019 10:29 am

Thanks for the heads up.

Ijor and I have been chatting a lot over the years. I worked on a 68000 die extraction as well - I have a transistor level netlist and schematic. Ijor beat me with the hard work of actually producing a core, and it's fantastic.

I do an FX variant for the A500:
https://github.com/FPGAArcade/replay_re ... ster/amiga


It would be nice to get a cycle accurate 020 for the A1200, but I think the focus is on high speed 20+ yeah.
/Mike

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Re: Work on the Minimig core?

Postby slingshot » Fri Nov 08, 2019 1:56 pm

Meanwhile I've created a branch with Tobias' repo (even enabled HW multiplier: caused slight performance increase according to Sysinfo):
https://github.com/mist-devel/minimig-m ... e/tobiflex

@retrofun (and others), maybe would be better to send PR's directly to that repo? Then this branch can be merged to master. Or any other ideas? I'm sure it's not a good idea to maintain two TG68K repos.

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Re: Work on the Minimig core?

Postby slingshot » Fri Nov 08, 2019 2:18 pm

tobiflex wrote:The TG68K has a big drawback. In the case of memory accesses, the address is generated only in the cycle in which the access also takes place by means of an addition. Therefore, the address is not valid immediately after the clock edge.

This means the problem is that the address output is not fully registered? I think there are a couple of CPU cores with this weakness then. Also a real 68000 asserts AS_N at least a half cycle after it places the address on the address bus (not sure about 68020).

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Re: Work on the Minimig core?

Postby MasterOfGizmo » Fri Nov 08, 2019 8:26 pm

fpgaarcade wrote:It would be nice to get a cycle accurate 020 for the A1200, but I think the focus is on high speed 20+ yeah.


Not sure what demand there is for a cycle exact 020. Basically all machines that introduced the 020 came in various speeds and even 030 variants. So at that time people stopped to rely on accuracy, anyway. May also be related to the caches which make things rather unpredictable anyway. So yes, i also think that for 020 people will want speed over accuracy.
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Re: Work on the Minimig core?

Postby Lroby74 » Fri Nov 08, 2019 11:03 pm

MasterOfGizmo wrote:i also think that for 020 people will want speed over accuracy.

I talk for me now, but i prefer a perfect FPGA version of a normal car like Mazda2 rather than a FPGA not accurate version of a Porsche
i mean i would prefer a 100% accurate 68020 14 mhz cpu (same ad real A1200) respect to a 100 mhz virtual 020 cpu..
FPGA for me is overall accuracy on real machines hardware reproducion

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Re: Work on the Minimig core?

Postby apolkosnik » Fri Nov 08, 2019 11:16 pm

Lroby74 wrote:
MasterOfGizmo wrote:i also think that for 020 people will want speed over accuracy.

I talk for me now, but i prefer a perfect FPGA version of a normal car like Mazda2 rather than a FPGA not accurate version of a Porsche
i mean i would prefer a 100% accurate 68020 14 mhz cpu (same ad real A1200) respect to a 100 mhz virtual 020 cpu..
FPGA for me is overall accuracy on real machines hardware reproducion

Just think of it as a custom Porsche with an V8 from a Ferrari ;-)

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Re: Work on the Minimig core?

Postby ex68k » Sat Nov 09, 2019 1:58 pm

Lroby74 wrote:
MasterOfGizmo wrote:i also think that for 020 people will want speed over accuracy.

I talk for me now, but i prefer a perfect FPGA version of a normal car like Mazda2 rather than a FPGA not accurate version of a Porsche
i mean i would prefer a 100% accurate 68020 14 mhz cpu (same ad real A1200) respect to a 100 mhz virtual 020 cpu..
FPGA for me is overall accuracy on real machines hardware reproducion


Please don't mix up "accuracy" and "cycle exact".
Accuracy is the definitive goal,
Cycle exact execution doesn't really make sense for CPUs with read buffers & caches anymore. So it is less and less important, if you climb up the ladder of '20, '30, '40 and '60 ...

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Re: Work on the Minimig core?

Postby fpgaarcade » Sat Nov 09, 2019 9:00 pm

slingshot wrote:Meanwhile I've created a branch with Tobias' repo (even enabled HW multiplier: caused slight performance increase according to Sysinfo):
https://github.com/mist-devel/minimig-m ... e/tobiflex

@retrofun (and others), maybe would be better to send PR's directly to that repo? Then this branch can be merged to master. Or any other ideas? I'm sure it's not a good idea to maintain two TG68K repos.


I thought the plan was to treat TB's repos as master
https://github.com/TobiFlex/TG68K.C

and we each maintain our own copies as required. It's a shame there isn't an easier way to have inter-repos dependencies- or should we brave submodule?


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