Search found 2315 matches

by ijor
Sun Dec 10, 2017 1:23 pm
Forum: MiSTer
Topic: SDRAM board
Replies: 49
Views: 2302

Re: SDRAM board

It might be possible to use the CKE pin.
by ijor
Sun Dec 10, 2017 1:19 pm
Forum: Hardware
Topic: MEGAFILE 60 disk capacity issue
Replies: 6
Views: 247

Re: MEGAFILE 60 disk capacity issue

I don't think that "RLL uses the same density as MFM." is good formulation. Even if flux density (or whatever is proper term) on surface might be same, structure is different. Encoding is of course different by definition. So what? What matters here is the transition density/frequency at ...
by ijor
Sun Dec 10, 2017 2:11 am
Forum: Hardware
Topic: MEGAFILE 60 disk capacity issue
Replies: 6
Views: 247

Re: MEGAFILE 60 disk capacity issue

Most MFM drives can work with RLL without problems. RLL uses the same density as MFM. Those MFM drives were manufactured before RLL controllers reached the market. They just weren't factory tested with RLL.
by ijor
Sun Dec 10, 2017 2:05 am
Forum: MiSTer
Topic: SDRAM board
Replies: 49
Views: 2302

Re: SDRAM board

SRAM could be a nice addition. If going to high speed SRAM, personally, I prefer synchronous and not asynchronous. It should be possible to use a single board sharing the buses and just use separate chip select signals. Even if they won't be used both by the same core, it is still more convenient th...
by ijor
Sun Dec 10, 2017 1:59 am
Forum: MiSTer
Topic: MISTer on DE0-nano?
Replies: 48
Views: 1621

Re: MISTer on DE0-nano?

Perhaps more important than changing the constrains is to adjust the PLL clock shift. The ideal shift depends on several factors. You might also try using a dedicated clock output pin if it reaches a reasonable location on the GPIO connector. The AS4C16M16SA-6TCN is certainly outstanding. You need a...
by ijor
Sun Dec 10, 2017 1:53 am
Forum: Coding
Topic: SHIFTER reimplementation on FPGA
Replies: 16
Views: 455

Re: SHIFTER reimplementation on FPGA

Ah. You should test it first. It is more important to run Spectrum 512 than the couple of demos that need an advanced Shifter model. Spectrum changes the palette on the fly. You might need to fine tune your timing.

It is here: http://www.atarimania.com/utility-atari ... 22312.html
by ijor
Sat Dec 09, 2017 3:46 pm
Forum: Coding
Topic: SHIFTER reimplementation on FPGA
Replies: 16
Views: 455

Re: SHIFTER reimplementation on FPGA

I think the problem is when you're doing register writes mid-scanline, it's triggering reset because LOAD and CS are asserted together. I don't think this is really happening but the signal on the FPGA (combinatorial) is getting triggered. I would suspect that the problem is something else. Does Sp...
by ijor
Sat Dec 09, 2017 5:04 am
Forum: Coding
Topic: SHIFTER reimplementation on FPGA
Replies: 16
Views: 455

Re: ST Chipset decap

I added schematics for the original clock generator here: http://atari-forum.com/viewtopic.php?f=16&t=29658&p=333893#p333893 Note that it uses a simple combinatorial mux, exactly what we recommended not to do. But an old school ASIC is completely different than a modern FPGA. And this is pre...
by ijor
Sat Dec 09, 2017 4:56 am
Forum: Coding
Topic: ST Chipset decap
Replies: 95
Views: 18575

Re: ST Chipset decap

SHIFTER clock generator: ShifterClockGen.jpg The top circuit is supposed to generate a power up signal ( nPor ). It is a clever and tricky circuit with the clock and reset connected with the roles inverted (clock as reset and reset as clock). But I don't think it works always. Not big deal if it doe...
by ijor
Fri Dec 08, 2017 1:43 pm
Forum: Coding
Topic: ST Chipset decap
Replies: 95
Views: 18575

Re: ST Chipset decap

I moved all the posts related to reimplementing SHIFTER on a modern FPGA to a new topic:

viewtopic.php?f=16&t=32747#p333724
by ijor
Fri Dec 08, 2017 3:12 am
Forum: Coding
Topic: SHIFTER reimplementation on FPGA
Replies: 16
Views: 455

Re: ST Chipset decap

I don't think skew would be much of a problem - it would have to reach quite a big delay to affect anything, ... No, the problem with clock skew is usually not setup timing, but hold timing. A minimum clock skew might be enough to create hold timing violations. I have had everything derived from th...
by ijor
Thu Dec 07, 2017 12:03 pm
Forum: Coding
Topic: SHIFTER reimplementation on FPGA
Replies: 16
Views: 455

Re: ST Chipset decap

I forgot to mention it but I also clear all the registers at the start of each DE, so each line begins fresh on the first LOAD after DE. That's still how you do it? Or that was only on the original, simple, implementation? Because resetting the line logic unconditionally like that will break Closur...
by ijor
Thu Dec 07, 2017 4:06 am
Forum: Coding
Topic: SHIFTER reimplementation on FPGA
Replies: 16
Views: 455

Re: ST Chipset decap

It just sycnhronises scanlines to DE, and loads RR from IR every 4th LOAD. Depending the exact meaning of the above sentence, I'm not sure that's the best way. It might be better to synchronize to the first LOAD pulse as the real Shifter does. If you follow DE you might get into some wakeup issues....
by ijor
Thu Dec 07, 2017 1:43 am
Forum: Coding
Topic: SHIFTER reimplementation on FPGA
Replies: 16
Views: 455

Re: ST Chipset decap

My verilog implementation isn't able to run {Closure} properly still, so I'm trying to work out what is different from the real IC. I thought you were taking the digital outputs from Shifter, but I guess you want to replace Shifter altogether, that's nice :) Well, I can't say why your implementatio...
by ijor
Thu Dec 07, 2017 12:45 am
Forum: Coding
Topic: ST Chipset decap
Replies: 95
Views: 18575

Re: ST Chipset decap

Smonson wrote:Where does pixCtrLoad go?


You can ignore it. See my elaboration in this message: viewtopic.php?f=16&t=29658&start=25#p293030

Edit: Feel free to ask if you would like more details.
by ijor
Wed Dec 06, 2017 3:35 am
Forum: MiSTer
Topic: MISTer on DE0-nano?
Replies: 48
Views: 1621

Re: MISTer on DE0-nano?

It will produce around the same amount of heat because the source of heat is HPS part (ARM) which is exactly the same on both chips. I know, but I think we agreed that, at least partially, the heating is a consequence of the proximity of other components. Anyway, my point is that even if producing ...
by ijor
Wed Dec 06, 2017 12:57 am
Forum: MiSTer
Topic: SDRAM board
Replies: 49
Views: 2302

Re: SDRAM board

If drive power (I/O lines) is truly a concern then I can use bi-directional buffers and tri-state each SDRAM when not being accessed. People have asked me if I would make a memory board with at least 64MB on it, so I am asking if I design and build the boards could it be supported by MiSTer? Ideall...
by ijor
Wed Dec 06, 2017 12:45 am
Forum: MiSTer
Topic: MISTer on DE0-nano?
Replies: 48
Views: 1621

Re: MISTer on DE0-nano?

I just noted that the DE0 has a different FPGA grade than the DE10. The FPGA on the DE10 is I7 , on the DE0 is C6 . C type FPGA has a smaller temperature range. That means that if the DE0 has the same heating problems as the DE10 (btw, would be interested to know), then cooling might be more critica...
by ijor
Wed Dec 06, 2017 12:40 am
Forum: Hardware
Topic: How I found some original Atari ST ASIC designs
Replies: 79
Views: 9807

Re: How I found some original Atari ST ASIC designs

Steven Seagal wrote:As I've started writing the video logic in C, I was wondering if you could give us the high resolution values in comparators for BLANK, horizontal and vertical, on the STF, if you have them?


Give me a few days. If I forget, don't hesitate to remind me :)
by ijor
Mon Dec 04, 2017 12:54 pm
Forum: MiSTer
Topic: MISTer on DE0-nano?
Replies: 48
Views: 1621

Re: MISTer on DE0-nano?

And since all these boards are from Terasic, it's more likely they use the same peripheral chips. I was confident that Linux part should work on DE0-nano SocKit. It also should work on DE1-SoC and DE10-standard. Yes, it makes sense and that's what I thought. Just wondering why they have separate bu...
by ijor
Mon Dec 04, 2017 12:15 pm
Forum: MiSTer
Topic: MISTer on DE0-nano?
Replies: 48
Views: 1621

Re: MISTer on DE0-nano?

- installed sd card with (Main_)MiSTer (latest one from releases directory). Linux booted MiSTer was executed ... Btw, I wonder if the U-boot and the preloader are fully portable. Obviously it works, and I guess that's because the main boot parameters, the DRAM type and the main clock are identical...
by ijor
Mon Dec 04, 2017 2:14 am
Forum: MiSTer
Topic: MISTer on DE0-nano?
Replies: 48
Views: 1621

Re: MISTer on DE0-nano?

There is a VGA enable pin. Did you connect it? Otherwise you might need to modify the code to ignore it and output to the VGA unconditionally.
by ijor
Thu Nov 30, 2017 4:55 pm
Forum: Hardware
Topic: How I found some original Atari ST ASIC designs
Replies: 79
Views: 9807

Re: How I found some original Atari ST ASIC designs

I was thinking about the DPR ref. PT030 in Sheet 29 that gets the "start line" decision as input. The counter (NLCBN, etc.) and this DPR being clocked by the same line, when the counter matches it's too late to be output, the result is held until next clock. If that's true, then we find 4...
by ijor
Thu Nov 30, 2017 4:48 pm
Forum: Coding
Topic: ST Chipset decap
Replies: 95
Views: 18575

Re: ST Chipset decap

About the delay between "first LOAD after DE" and "pixel counter starts running" we see on the simulations, I was wondering if it was a delay of about 2 CPU cycles, or 2 pixel clocks, which would be shorter in time units at higher resolution? It is pixel clocks. In the simulatio...
by ijor
Thu Nov 30, 2017 12:23 pm
Forum: Coding
Topic: ST Chipset decap
Replies: 95
Views: 18575

Re: ST Chipset decap

I apologise if this is a silly question, but what is nReset connected to on an STFM shifter which has no hardware reset? Both SHIFTER and MMU do have hardware reset even when lacking a dedicated reset pin. They internally generate a reset when the external signals are at a specific invalid conditio...

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