Search found 57 matches

by Alynna
Tue Feb 12, 2019 4:49 pm
Forum: MiSTer
Topic: Version control for Sys
Replies: 5
Views: 1381

Re: Version control for Sys

I would like to see a github repo that has just the stuff from sys and stuff around it required to start a new core or port on MiSTer. Could we get that?
by Alynna
Fri Feb 08, 2019 2:19 pm
Forum: MiSTer
Topic: Would MiSTer ever be able to run a Neo Geo core?
Replies: 101
Views: 40225

Re: Would MiSTer ever be able to run a Neo Geo core?

This is not working yet, but I am confident I will get it working, but I wanted to share where I am going with DDR3 access. This is the code (so far) for my BRAM cached DDR3 controller. The current code uses 128K of BRAM for cache in 1KB pages. It commits and reads 1K pages in 128 byte bursts (or w...
by Alynna
Fri Feb 08, 2019 12:28 am
Forum: MiSTer
Topic: Would MiSTer ever be able to run a Neo Geo core?
Replies: 101
Views: 40225

Re: Would MiSTer ever be able to run a Neo Geo core?

This is not working yet, but I am confident I will get it working, but I wanted to share where I am going with DDR3 access. This is the code (so far) for my BRAM cached DDR3 controller. The current code uses 128K of BRAM for cache in 1KB pages. It commits and reads 1K pages in 128 byte bursts (or wi...
by Alynna
Tue Jan 29, 2019 4:13 pm
Forum: MiSTer
Topic: Minimig (Amiga) core discussion
Replies: 799
Views: 152414

Re: Minimig (Amiga) core discussion

Yeah only the CPU can access it, but (at least in this core) if I do a ram test it works for around 4MB at once, but it keeps the CPU off the bus for too long for longer transfers. Or maybe its holding the DDR bus for too long. My new ddram.sv i'm working on will give time back to the core during tr...
by Alynna
Mon Jan 28, 2019 5:27 pm
Forum: MiSTer
Topic: Minimig (Amiga) core discussion
Replies: 799
Views: 152414

Re: Minimig (Amiga) core discussion

Also for core writers: I am writing a new ddram.sv which should become the gold standard for DDRAM access that I hope will be able to be used in any core. I'm planning on featuring: ⋅ Separate read/write caches ⋅ Basic pipelining (don't know how much yet but probably 16 bytes wri...
by Alynna
Mon Jan 28, 2019 5:11 pm
Forum: MiSTer
Topic: Minimig (Amiga) core discussion
Replies: 799
Views: 152414

Re: Minimig (Amiga) core discussion

Here is my BETA BUILD for 256MB RAM expansion. https://github.com/alynna/Minimig-AGA_MiSTer/blob/MiSTer/output_files/Minimig.rbf Known bugs: 1) Reliable to at least 4MB of constant transfer at once. Maybe more, but 16mb may lead to a crash due to the CPU being off the bus for too long. 2) Screen go...
by Alynna
Mon Jan 28, 2019 5:02 pm
Forum: MiSTer
Topic: Minimig (Amiga) core discussion
Replies: 799
Views: 152414

Re: Minimig (Amiga) core discussion

Here is my BETA BUILD for 256MB RAM expansion. https://github.com/alynna/Minimig-AGA_MiSTer/blob/MiSTer/output_files/Minimig.rbf Known bugs: 1) Reliable to at least 4MB of constant transfer at once. Maybe more, but 16mb may lead to a crash due to the CPU being off the bus for too long. 2) Screen goe...
by Alynna
Sun Jan 27, 2019 9:36 am
Forum: MiSTer
Topic: Minimig (Amiga) core discussion
Replies: 799
Views: 152414

Re: Minimig (Amiga) core discussion

I think I will have the 256M RAM expansion done soon. I have also been coding the infrastructure around RTG RAM wise since its based on the same code (its just another RAM instantiation)
by Alynna
Wed Jan 23, 2019 7:51 pm
Forum: MiSTer
Topic: Minimig (Amiga) core discussion
Replies: 799
Views: 152414

Re: Minimig (Amiga) core discussion

Sorgelig wrote:You cannot add ram3 as there is no more free MPFE ports left.
You can remove Linux audio support while working on RTG. When you will finish RTG, i will help you to integrate Linux audio.

I need some help with some things is there any place I can chat you like telegram or discord?
by Alynna
Wed Jan 23, 2019 7:31 pm
Forum: MiSTer
Topic: Minimig (Amiga) core discussion
Replies: 799
Views: 152414

Re: Minimig (Amiga) core discussion

Also I just synced to the master source and I am not sure how to resolve this conflict: <<<<<<< HEAD //Spare 64-bit DDR3 RAM access //Hooked to RTG card .ramclk2_clk(rtg_clk), .ram2_address(rtg_address), .ram2_burstcount(rtg_burstcount), .ram2_waitrequest(rtg_waitrequest), .ram2_readdata(rtg_readdat...
by Alynna
Wed Jan 23, 2019 7:12 pm
Forum: MiSTer
Topic: Minimig (Amiga) core discussion
Replies: 799
Views: 152414

Re: Minimig (Amiga) core discussion

For those interested in these types of things, heres a little preliminary on what the ethernet will look like: // MiniMig-Net - type Zorro II - Mapping probably $E8xxxx // - type C64-IO - Mapping $DFxx // - other cores to be determined Offset Size 0000 01 (READ) Status register 7-6: 11=24/32 bit mod...
by Alynna
Tue Jan 22, 2019 5:04 pm
Forum: MiSTer
Topic: Minimig (Amiga) core discussion
Replies: 799
Views: 152414

Re: Minimig (Amiga) core discussion

So what's the official right numbers for these settings? if it's about SDC, then keep it as is. At least for now. It is about the timing thing, the setup/hold. Using 4/4 right now, should it be 4/3? Also if I make the changes to the main MiSTer code to support the tap0 device, will you be able to i...
by Alynna
Tue Jan 22, 2019 1:36 pm
Forum: MiSTer
Topic: Minimig (Amiga) core discussion
Replies: 799
Views: 152414

Re: Minimig (Amiga) core discussion

So what's the official right numbers for these settings?

Also if I make the changes to the main MiSTer code to support the tap0 device, will you be able to integrate them into the mainline?
by Alynna
Sat Jan 19, 2019 9:05 pm
Forum: MiSTer
Topic: Minimig (Amiga) core discussion
Replies: 799
Views: 152414

Re: Minimig (Amiga) core discussion

A tap device is a linux virtual ethernet device. You can make them with the command: ip tuntap add mode tap tap0 And remove likewise: ip tuntap del tap0 When it is made, then Linux creates a device file like /dev/tun/tap0 and also an ethernet adapter is made "tap0" You can then open the de...
by Alynna
Sat Jan 19, 2019 6:22 pm
Forum: MiSTer
Topic: Minimig (Amiga) core discussion
Replies: 799
Views: 152414

Re: Minimig (Amiga) core discussion

OBTW on the HPS side could we please get a tap0 network device bridged to the main ethernet device? I am planning on adding network support. This will be useful on all cores. It will probably need the linux bridging package, and maybe a kernel config change. If this is already supported never mind m...
by Alynna
Sat Jan 19, 2019 3:59 pm
Forum: MiSTer
Topic: Minimig (Amiga) core discussion
Replies: 799
Views: 152414

Re: Minimig (Amiga) core discussion

thanks and thanks for your patience with my stupid n00b questions and ideas. I am trying to learn this.
by Alynna
Sat Jan 19, 2019 3:11 pm
Forum: MiSTer
Topic: Minimig (Amiga) core discussion
Replies: 799
Views: 152414

Re: Minimig (Amiga) core discussion

The biggest problem with minimig is that the TG68k runs on 114 MHz. This needs to be constrained in the SDC with some multicycle paths, since it's impossible to have such high clock for the CPU. This one did the job on MiST: set_multicycle_path -from {TG68K:tg68k|TG68KdotC_Kernel:pf68K_Kernel_inst|...
by Alynna
Sat Jan 19, 2019 2:24 pm
Forum: MiSTer
Topic: Minimig (Amiga) core discussion
Replies: 799
Views: 152414

Re: Minimig (Amiga) core discussion

though I think I can sync both the 28 and 7 mhz clock by deriving them both from the SDRAM clock and dividing the 114/4 to 28 and the 114/16=7.16. Since they will be being divided at the same time.... they should be in perfect sync right?
by Alynna
Sat Jan 19, 2019 2:19 pm
Forum: MiSTer
Topic: Minimig (Amiga) core discussion
Replies: 799
Views: 152414

Re: Minimig (Amiga) core discussion

yes i am very interested please upload to github
by Alynna
Sat Jan 19, 2019 2:13 pm
Forum: MiSTer
Topic: Minimig (Amiga) core discussion
Replies: 799
Views: 152414

Re: Minimig (Amiga) core discussion

You've made things only worse. The clocks you've created are called asynchronous clocks. This is worst thing you can do for clocks :) You will see Quartus warnings about signals used as clocks without declaration. You may describe these clocks in SDC file, so Quartus won't complain. But it is great...
by Alynna
Sat Jan 19, 2019 1:37 pm
Forum: MiSTer
Topic: Minimig (Amiga) core discussion
Replies: 799
Views: 152414

Re: Minimig (Amiga) core discussion

Nope. How you imagine the clock multiplication? This is against the physics. PLL is used for multiplication but it's virtual multiplication. Actually it's still division of much higher clock. You can use PLL to make 114 from 28, but it will be even worse than current case. The only way to simplify ...
by Alynna
Sat Jan 19, 2019 12:31 pm
Forum: MiSTer
Topic: Minimig (Amiga) core discussion
Replies: 799
Views: 152414

Re: Minimig (Amiga) core discussion

so heres a question, is it possible to create a 114mhz clock from the 28mhz clock by multiplying it by 4? Then we'll just have the 28mhz clock and everything will be in sync. Because I am sure there are plenty of rising/falling edge tricks being played, but down at 7mhz which is being derived by the...
by Alynna
Fri Jan 18, 2019 3:30 pm
Forum: MiSTer
Topic: Minimig (Amiga) core discussion
Replies: 799
Views: 152414

Re: Minimig (Amiga) core discussion

so far my experience is that I have had a bad build about 1 out of every 4 tries, but the differences I can see are these: 1) I'm using quatrus 18.1 lite 2) I am using 14.31818mhz synced clocks I am now using seed 47 but I also understand what you are talking about that being a moving target. You sh...
by Alynna
Fri Jan 18, 2019 3:40 am
Forum: MiSTer
Topic: Minimig (Amiga) core discussion
Replies: 799
Views: 152414

Re: Minimig (Amiga) core discussion

I just committed all my source changes to my repo if you want to look at them. that Minimig.rbf core is functional but do NOT use it for anything important yet. the 256MB expansion right now is just a 512K ringbuffer at 1F80000 and memory WILL start to corrupt at the 23.5mb SDRAM mark. The next phas...
by Alynna
Fri Jan 18, 2019 2:57 am
Forum: MiSTer
Topic: Minimig (Amiga) core discussion
Replies: 799
Views: 152414

Re: Minimig (Amiga) core discussion

1 produced an unstable build. BUT! I will run the design space explorer overnight and find us a great seed.

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