Atari-Forum

There you go. Some money delivered.

No. The pixel clock it's 16 Mhz at medium and 32 Mhz at high. It would be reasonable to assume that the internal 16MHz (and 8MHz) are directly derived from the 32MHz clock, and to be mostly in phase with each other, right (i.e. just divided down)? With the waveforms in http://atari-forum.com/viewto...

The DFF that generates the signals in this case, it is some sort of combination of a DFF and an RS async latch, rather unusual. If both async signals are asserted at the same, both outputs are asserted. In that case the mux would OR both inputs. But the async reset is asserted only during hardware ...

ijor wrote:SHIFTER shift registers reload control logic schematics (now complete):

Nice. I'm guessing the lower Q's on the DFF's up on top are really the !Q's, but what's the role of the pxCtrLoad signal?