Search found 124 matches

by Smonson
Thu Oct 18, 2018 9:40 am
Forum: Hardware
Topic: STFM to DVI/HDMI project
Replies: 85
Views: 9141

Re: STFM to DVI/HDMI project

Possibly a bit of overbleed from bright pixels into the adjacent ones would also look good? I actually don't own a CRT to study how it really looks.
by Smonson
Thu Oct 18, 2018 9:38 am
Forum: Hardware
Topic: STFM to DVI/HDMI project
Replies: 85
Views: 9141

Re: STFM to DVI/HDMI project

Cyprian wrote:Would be possible to add one feature - scanline mode?


Yep, easy. I've got that planned. Do you think just darkening every second line is the best approach?
by Smonson
Wed Oct 17, 2018 11:38 pm
Forum: Hardware
Topic: STFM to DVI/HDMI project
Replies: 85
Views: 9141

Re: STFM to DVI/HDMI project

A few people are testing prototypes out. I think the next hardware revision will be the first "official" one and I will start making a few of them up for people who want one. Your shifter must be in a socket to be able to install this mod, by the way.
by Smonson
Tue Oct 16, 2018 11:53 am
Forum: Hardware
Topic: STFM to DVI/HDMI project
Replies: 85
Views: 9141

Re: STFM to DVI/HDMI project

Yeah, I can sychronise the line timing to either a long gap between DEs (only for standard modes) or VSYNC. FYI - I have implemented this today. If vsync is connected, then it will use that, otherwise it will use the first DE of each frame as a replacement for vsync. That should make it easier to i...
by Smonson
Wed Oct 03, 2018 8:20 am
Forum: For sale / Wanted
Topic: RARE VINTAGE ATARI 520 STFM COMPUTER
Replies: 15
Views: 1016

Re: RARE VINTAGE ATARI 520 STFM COMPUTER

In Australia, the oft-quoted saying is "...tell him he's dreamin'".
by Smonson
Wed Aug 15, 2018 2:47 am
Forum: Coding
Topic: SHIFTER reimplementation on FPGA
Replies: 78
Views: 8338

Re: SHIFTER reimplementation on FPGA

I didn't test without it, but I had a huge amount of noise on my original prototype (that used stripboard) to the point where it rarely functioned. With the 3.3v clock passing through an unshielded ribbon cable, it seems worth having it. It's only a 40c part, and it's tiny (3x2.5mm), so not too many...
by Smonson
Tue Aug 14, 2018 10:30 pm
Forum: Coding
Topic: SHIFTER reimplementation on FPGA
Replies: 78
Views: 8338

Re: SHIFTER reimplementation on FPGA

I'm using a transceiver (74ALVC164245) for the data bus. The 5-to-3.3 shifters are 74LVC245s and the 16MHz clock is buffered at the socket with an MC74VHC1GT125.
by Smonson
Fri Aug 10, 2018 4:38 am
Forum: Coding
Topic: SHIFTER reimplementation on FPGA
Replies: 78
Views: 8338

Re: SHIFTER reimplementation on FPGA

Hmm, I see. I'll leave that problem for later since it seems quite intractable.
by Smonson
Fri Aug 10, 2018 3:01 am
Forum: Coding
Topic: SHIFTER reimplementation on FPGA
Replies: 78
Views: 8338

Re: SHIFTER reimplementation on FPGA

Thanks Troed, I only have the one machine. I'm still not understanding what the problem is though. If the chipset reset skew is related to the MMU/GLUE, then won't it just be another symptom of the wakeup states we already have to compensate for?
by Smonson
Thu Aug 09, 2018 10:53 am
Forum: Hardware
Topic: The SECRET VIDEO MODE in an ST: 400 lines in COLOR (and with 72 Hz)!
Replies: 81
Views: 10695

Re: The SECRET VIDEO MODE in an ST: 400 lines in COLOR (and with 72 Hz)!

...I take back what I said about 320x200x256 being impossible.
by Smonson
Thu Aug 09, 2018 10:28 am
Forum: Coding
Topic: SHIFTER reimplementation on FPGA
Replies: 78
Views: 8338

Re: SHIFTER reimplementation on FPGA

Oh man, I was completely wrong about fitting this into a MAX 7000 CPLD. It does fit into a 100-pin MAX V, but that's the only Altera CPLD architecture supported by Quartus-II that it's able to fit into (421 LEs). They're not 5v devices, and the TQFP-100 is a big package (14x14mm). So to make a stand...
by Smonson
Thu Aug 09, 2018 3:25 am
Forum: Coding
Topic: SHIFTER reimplementation on FPGA
Replies: 78
Views: 8338

Re: SHIFTER reimplementation on FPGA

I haven't published the latest one yet. It's done like this: // Generate 16MHz and 8MHz pixel clocks from 32MHz clock always @(posedge CLOCK_32) begin if (reset) begin speed_divider <= 0; end else begin speed_divider <= speed_divider + 2'b1; end end
by Smonson
Thu Aug 09, 2018 3:21 am
Forum: Hardware
Topic: The SECRET VIDEO MODE in an ST: 400 lines in COLOR (and with 72 Hz)!
Replies: 81
Views: 10695

Re: The SECRET VIDEO MODE in an ST: 400 lines in COLOR (and with 72 Hz)!

Curious, could something be tricked into using this in 640x200(Medium Resolution) but tricking it to Mono for 31khz? Thus eliminating the need for Monitors that support 15khz? If it's 200 colour lines, then it'll only be 15KHz. The 400 mono lines are faster because they only have half the amount of...
by Smonson
Wed Aug 08, 2018 4:22 am
Forum: Coding
Topic: SHIFTER reimplementation on FPGA
Replies: 78
Views: 8338

Re: SHIFTER reimplementation on FPGA

You can measure the wakeup with a Logic Analyzer as I described in the other thread. It is also possible to "visualize" (more or less) the wakeup with a screen that mixes low and med rez. I don't have a logic analyser, so I can't measure it. I have a scope, but that's a pretty unwieldy so...
by Smonson
Wed Aug 08, 2018 3:37 am
Forum: Coding
Topic: SHIFTER reimplementation on FPGA
Replies: 78
Views: 8338

Re: SHIFTER reimplementation on FPGA

But again, you must compare with a real SHIFTER. Some demos do have problems with a real SHIFTER depending on the wakeup. So your implementation is not necessarily wrong. Yeah, I don't think there's a problem with the model, but I like to rule it out. I have no way of seeing which wake-up state the...
by Smonson
Wed Aug 08, 2018 3:24 am
Forum: Coding
Topic: SHIFTER reimplementation on FPGA
Replies: 78
Views: 8338

Re: SHIFTER reimplementation on FPGA

How about MAX 7000 EPM7064
- TQFP-44
- 5v operation
- 36 user IOs
- 175MHz max
- 64 macrocells / 1250 gates
by Smonson
Tue Aug 07, 2018 10:59 pm
Forum: Coding
Topic: SHIFTER reimplementation on FPGA
Replies: 78
Views: 8338

Re: SHIFTER reimplementation on FPGA

I can send you an image if you want. But this is really not related to SHIFTER. It is just that the code assumes a fixed scan line length, 508 or 512 cycles in each case, when keeping sync with the video display. That's why you get that "slanted" diagonal distortion. Each scan line it get...
by Smonson
Tue Aug 07, 2018 10:53 pm
Forum: Coding
Topic: SHIFTER reimplementation on FPGA
Replies: 78
Views: 8338

Re: SHIFTER reimplementation on FPGA

ijor wrote:Are you sure the MAX V family is 5V tolerant?


Ah, you guys are right, only a couple of the huge ones are. Just pick basically any small 5v device. Off the top of my head I think 35 IOs are needed, plus a clock input.

One that would physically fit inside the PDIP-40 outline would be ideal.
by Smonson
Tue Aug 07, 2018 5:21 am
Forum: Hardware
Topic: Vertical white stripes when using a ST to VGA cable
Replies: 12
Views: 1095

Re: Vertical white stripes when using a ST to VGA cable

It's always a pleasure if I can assist in fixing something!
by Smonson
Mon Aug 06, 2018 11:25 pm
Forum: Coding
Topic: SHIFTER reimplementation on FPGA
Replies: 78
Views: 8338

Re: SHIFTER reimplementation on FPGA

I will soon (it's midnight here) but it's definitely working at 50 and broken at 60. Maybe they released different versions of the program, or someone modified the copy I have...Here's the disk: Indeed, this version is the other way around than the one I know, that works correctly only on 60Hz. Int...
by Smonson
Mon Aug 06, 2018 11:24 pm
Forum: Coding
Topic: SHIFTER reimplementation on FPGA
Replies: 78
Views: 8338

Re: SHIFTER reimplementation on FPGA

Hi Smonson, On this forum we have seen a number of STs over the years with Shifter chips that have failed. I don't know why chips like that fail over time - can semiconductor junctions fail? What causes that? Since the Shifter is a custom chip do you think an FPGA version would be available for gen...
by Smonson
Sun Aug 05, 2018 2:00 pm
Forum: Coding
Topic: SHIFTER reimplementation on FPGA
Replies: 78
Views: 8338

Re: SHIFTER reimplementation on FPGA

I will soon (it's midnight here) but it's definitely working at 50 and broken at 60. Maybe they released different versions of the program, or someone modified the copy I have.
by Smonson
Sun Aug 05, 2018 10:22 am
Forum: Hardware
Topic: Vertical white stripes when using a ST to VGA cable
Replies: 12
Views: 1095

Re: Vertical white stripes when using a ST to VGA cable

In low res mode, the shifter outputs pixels at 8MHz, same as the CPU clock speed, so 500KHz is every 16 pixels. At 50Hz, the length of each scanline is an exact multiple of 16 pixels (512 = 320 for the normal video plus 192 for borders). It's not exact in 60Hz though - I think you'd get diagonal lin...
by Smonson
Sun Aug 05, 2018 8:32 am
Forum: Coding
Topic: SHIFTER reimplementation on FPGA
Replies: 78
Views: 8338

Re: SHIFTER reimplementation on FPGA

Here are pics of Spectrum 512 running on a physical shifter (-38A) for comparison: At 50Hz: http://smonson.com/unmanaged/atari/IMAG0201.jpg At 60Hz: http://smonson.com/unmanaged/atari/IMAG0203.jpg And this is the FPGA model over HDMI at 50Hz (with starburst image loaded): http://smonson.com/unmanage...

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