Search found 452 matches

by Sorgelig
Wed Mar 22, 2017 6:18 am
Forum: ST(E) Clones (Suska / MiST)
Topic: Genesis / Megadrive core ported to MiST
Replies: 97
Views: 7786

Re: Genesis / Megadrive core ported to MiST

jotego wrote:

Code: Select all

Device   EP3C25E144C7


i think it's better to change to C8 part in project settings to help Quartus measure timings more correct.
MiST uses C8 grade of FPGA.
by Sorgelig
Tue Mar 21, 2017 10:31 pm
Forum: ST(E) Clones (Suska / MiST)
Topic: Jupiter Ace arrives at MiST
Replies: 33
Views: 1960

Re: Jupiter Ace arrives at MiST

It's community, and most development has been made for fun. Instead of walking around and sorting the cores, it would be good if more people will start to learn programming. Since FPGA has more circuit background than traditional programming, some users far from programming but good in circuits can ...
by Sorgelig
Mon Mar 20, 2017 5:41 pm
Forum: ST(E) Clones (Suska / MiST)
Topic: Jupiter Ace arrives at MiST
Replies: 33
Views: 1960

Re: Jupiter Ace arrives at MiST

Troubles aren't always come from RAM timings.
by Sorgelig
Mon Mar 20, 2017 5:34 pm
Forum: ST(E) Clones (Suska / MiST)
Topic: New feature: YPbPr/RGsB output
Replies: 66
Views: 4590

Re: New feature: YPbPr/RGsB output

Amiga core is a special case. Basically it generates "valid" video signals only when you choose standard PAL/NTSC modes. All other resolutions from Amiga core requires very special multisync monitor sold for Amiga computer. Even scalers won't accept these resolutions. The only way to outpu...
by Sorgelig
Mon Mar 20, 2017 5:30 pm
Forum: ST(E) Clones (Suska / MiST)
Topic: Genesis / Megadrive core ported to MiST
Replies: 97
Views: 7786

Re: Genesis / Megadrive core ported to MiST

Some cores I've seen have problems with one clock being derived (one clock divided to produce a slower clock) and then having hold timing issues. You should be able to see the failing paths on the timing report. These cases are usually not too difficult to fix. Ideally remove the clock division and...
by Sorgelig
Mon Mar 20, 2017 12:23 am
Forum: ST(E) Clones (Suska / MiST)
Topic: Jupiter Ace arrives at MiST
Replies: 33
Views: 1960

Re: Jupiter Ace arrives at MiST

Different people have different styles of programming. It doesn't mean other published sources are perfect. Neither is mine. Publishing the code means: 1) You respect the one from who you got the code. Remember, the original author spent a lot of time to develop it. 2) Some one can pick the code and...
by Sorgelig
Mon Mar 20, 2017 12:08 am
Forum: ST(E) Clones (Suska / MiST)
Topic: Genesis / Megadrive core ported to MiST
Replies: 97
Views: 7786

Re: Genesis / Megadrive core ported to MiST

However, we have a complex implementation of the Genesis core inherited from a different project. I do not quite understand why but the problem is that we are having many, many difficulties when trying to put the blocks together. Timing issues everywhere . This is a similar problem to what I found ...
by Sorgelig
Sat Mar 18, 2017 1:24 pm
Forum: ST(E) Clones (Suska / MiST)
Topic: Jupiter Ace arrives at MiST
Replies: 33
Views: 1960

Re: Jupiter Ace arrives at MiST

As always without sources... If he writes core whole by himself then it's ok. But he usually takes someone's work..
This is totally wrong behavior!
by Sorgelig
Tue Mar 14, 2017 6:42 am
Forum: ST(E) Clones (Suska / MiST)
Topic: Bomb Jack Arcade : Has someone tried to port this to the MiST ?
Replies: 5
Views: 569

Re: Bomb Jack Arcade : Has someone tried to port this to the MiST ?

MiST FPGA has 66(or 69? i forgot) BRAM blocks, although you can't compare BRAM blocks from different FPGA chips.
by Sorgelig
Wed Mar 08, 2017 10:28 pm
Forum: ST(E) Clones (Suska / MiST)
Topic: MiST VGA upscaling experiments
Replies: 127
Views: 25382

Re: MiST VGA upscaling experiments

Yes, i can see the whole pic. But i didn't test all cores. Only those on my repository.
by Sorgelig
Wed Mar 08, 2017 2:08 am
Forum: ST(E) Clones (Suska / MiST)
Topic: New feature: YPbPr/RGsB output
Replies: 66
Views: 4590

Re: New feature: YPbPr/RGsB output

It's impossible to adjust video on cores directly. It will break HW compatibility. Original ZX spectrum and C64 would have the same problem on your TV through YPbPr cable. Actually i'm not sure about C64 (it's not my core but i assume it's more or less compatible with original HW), but i'm 100% sure...
by Sorgelig
Tue Mar 07, 2017 3:09 am
Forum: ST(E) Clones (Suska / MiST)
Topic: Apollo Team announces developing of Vampire standalone version to run as AMIGA and ATARI ST
Replies: 396
Views: 38058

Re: Apollo Team announces developing of Vampire standalone version to run as AMIGA and ATARI ST

The ST chipset has plenty of cases that violate modern synchronous design rules. almost any real life digital circuit "violates" synchronous design. Actually it's not an issue as well and doesn't prevent making 1:1 replica using synchronous design. When you just come from traditional prog...
by Sorgelig
Mon Mar 06, 2017 10:11 am
Forum: ST(E) Clones (Suska / MiST)
Topic: Apollo Team announces developing of Vampire standalone version to run as AMIGA and ATARI ST
Replies: 396
Views: 38058

Re: Apollo Team announces developing of Vampire standalone version to run as AMIGA and ATARI ST

So-called tri-state buses of M68K are also two buses inside the chip. One input and one output. They are connected together to minimize amount of chip pins. Basically it's exactly what FPGA does.
by Sorgelig
Mon Mar 06, 2017 1:07 am
Forum: ST(E) Clones (Suska / MiST)
Topic: Apollo Team announces developing of Vampire standalone version to run as AMIGA and ATARI ST
Replies: 396
Views: 38058

Re: Apollo Team announces developing of Vampire standalone version to run as AMIGA and ATARI ST

Yes, Vampire works like that. Internally all function units use Altera or ARM defined bus. Nothing else. I have my information directly from developer. FPGA's cannot directly resemble (all) discrete logic 1:1 anyway, but only functional equivalents. E.g. there is no way to implement a truely tri-st...
by Sorgelig
Sat Mar 04, 2017 1:03 am
Forum: ST(E) Clones (Suska / MiST)
Topic: Apollo Team announces developing of Vampire standalone version to run as AMIGA and ATARI ST
Replies: 396
Views: 38058

Re: Apollo Team announces developing of Vampire standalone version to run as AMIGA and ATARI ST

1st1 wrote:What do you need?

to write emulator of other platform on Vampire, you will need a simple core source code where FPGA pins assignments and functions will be clearly visible.
by Sorgelig
Fri Mar 03, 2017 5:33 am
Forum: ST(E) Clones (Suska / MiST)
Topic: Apollo Team announces developing of Vampire standalone version to run as AMIGA and ATARI ST
Replies: 396
Views: 38058

Re: Apollo Team announces developing of Vampire standalone version to run as AMIGA and ATARI ST

Apollo didn't publish any SDK for 3rd party cores, so talking about emulation of other systems is nonsense until Apollo turn its face to users and 3rd part developers.
by Sorgelig
Wed Mar 01, 2017 10:41 pm
Forum: ST(E) Clones (Suska / MiST)
Topic: New MIST core: PC Engine!
Replies: 103
Views: 22420

Re: New MIST core: PC Engine!

You can check MiST schematic by yourself. HSync/VSync are LVTTL signals. They only can be in '1' state which is ~2.5V and '0' state which is 0V. It's true and equal for all cores. They go through 100 Ohm resistors. TV usually has 75 OHm pull down resistors on these signals make HSync/VSync 1/4 of or...
by Sorgelig
Wed Mar 01, 2017 1:03 pm
Forum: ST(E) Clones (Suska / MiST)
Topic: New MIST core: PC Engine!
Replies: 103
Views: 22420

Re: New MIST core: PC Engine!

I didn't see the code of PC engine, but such strange problems can happen if core uses async design. FPGA doesn't work well with async design (when some random signals used as a clocks).
VSync/HSync are logic signals, so resistors won't help you here.
by Sorgelig
Wed Mar 01, 2017 6:02 am
Forum: ST(E) Clones (Suska / MiST)
Topic: NEW OR UPDATED ARCADE CORES
Replies: 127
Views: 8947

Re: NEW OR UPDATED ARCADE CORES

May be problem not in copyrights... May be he was upset by something/someone.
by Sorgelig
Tue Feb 28, 2017 8:31 pm
Forum: ST(E) Clones (Suska / MiST)
Topic: Some coding questions......
Replies: 17
Views: 1531

Re: Some coding questions......

Yes, it's column/row selection. Actually SDRAM module is very simplified. I suggest to adapt my sram.sv module from ZX core. It supports whole SDRAM addressing.
by Sorgelig
Mon Feb 27, 2017 11:40 pm
Forum: ST(E) Clones (Suska / MiST)
Topic: Some coding questions......
Replies: 17
Views: 1531

Re: Some coding questions......

braincell1973 wrote:wire [12:0] run_addr =
(q == STATE_CMD_START)?{ 5'b00000, addr[15:8]}:{ 5'b00100, addr[7:0]};


res = condition ? choice_true : choice_false
this is pretty standard C style code. It's one-liner selector.
by Sorgelig
Mon Feb 27, 2017 12:18 pm
Forum: ST(E) Clones (Suska / MiST)
Topic: Apollo Team announces developing of Vampire standalone version to run as AMIGA and ATARI ST
Replies: 396
Views: 38058

Re: Apollo Team announces developing of Vampire standalone version to run as AMIGA and ATARI ST

Or get RPi for only fraction of Vampire price. It provides around the same level of emulation. Some UAE builds show crazy points in Sysinfo as well.
by Sorgelig
Sat Feb 25, 2017 2:13 am
Forum: ST(E) Clones (Suska / MiST)
Topic: MiST VGA upscaling experiments
Replies: 127
Views: 25382

Re: MiST VGA upscaling experiments

SuperBabyHix, It's true that many (if not all) cores output slightly out of TV standard freqs. Real PAL resolution is 312.5lines per field. I don't remember any core providing exactly 312.5lines(may be only Minimig - but i didn't check its code as it's too complicated). So if core provides only 312l...
by Sorgelig
Mon Feb 20, 2017 10:40 pm
Forum: ST(E) Clones (Suska / MiST)
Topic: Some coding questions......
Replies: 17
Views: 1531

Re: Some coding questions......

sorry, mistype.. Yes, it should be index[7:6]
File size is calculated by amount of bytes transferred.

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